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ManualsBrandsMICROCHIP TECHNOLOGY ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller SPDIP 28 16-Bit 40 null I/O number 21

 2010-2012 Microchip Technology Inc. DS80461G-page 1

dsPIC33FJ12MC201/202

The dsPIC33FJ12MC201/202 family devices that you

have received conform functionally to the current

Device Data Sheet (DS70265E), except for the

anomalies described in this document.

The silicon issues discussed in the following pages are

for silicon revisions with the Device and Revision IDs

listed in Table 1. The silicon issues are summarized in

Table 2.

The errata described in this document will be addressed

in future revisions of the dsPIC33FJ12MC201/202 silicon.

Data Sheet clarifications and corrections start on page 11,

following the discussion of silicon issues.

The silicon revision level can be identified using the

current version of MPLAB

IDE and Microchip’s

programmers, debuggers and emulation tools, which

are available at the Microchip corporate web site

(www.microchip.com).

For example, to identify the silicon revision level using

MPLAB IDE in conjunction with MPLAB ICD 3 or

PICkit™ 3:

1. Using the appropriate interface, connect the device

to the MPLAB ICD 3 programmer/debugger or

PICkit 3.

2. From the main menu in MPLAB IDE, select

onfigure>Select Device, and then select the

target part number in the dialog box.

3. Select the MPLAB hardware tool

(Debugger

>Select Tool).

4. Perform a “Connect” operation to the device

(Debugger

>Connect). Depending on the devel-

opment tool used, the part number and Device

Revision ID value appear in the Output window.

The Device and Revision ID values for the various

dsPIC33FJ12MC201/202 silicon revisions are shown

in Table 1.

Note: This document summarizes all silicon

errata issues from all revisions of silicon,

previous as well as current. Only the

issues indicated in the last column of

Table 2 apply to the current silicon

revision (A5).

Note: If you are unable to extract the silicon

revision level, please contact your local

Microchip sales office for assistance.

TABLE 1: SILICON DEVREV VALUES

Part Number Device ID

(1)

Revision ID for Silicon Revision

(2)

A2 A3 A4 A5

dsPIC33FJ12MC201 0x0800

0x3001 0x3002 0x3003 0x3005

dsPIC33FJ12MC202 0x0801

Note 1: The Device and Revision IDs (DEVID and DEVREV) are located at the last two implemented addresses in

program memory.

2: Refer to the “dsPIC33F/PIC24H Flash Programming Specification” (DS70152) for detailed information on

Device and Revision IDs for your specific device.

dsPIC33FJ12MC201/202 Family

Silicon Errata and Data Sheet Clarification

Summary of content (14 pages)

PAGE 1
dsPIC33FJ12MC201/202 dsPIC33FJ12MC201/202 Family Silicon Errata and Data Sheet Clarification The dsPIC33FJ12MC201/202 family devices that you have received conform functionally to the current Device Data Sheet (DS70265E), except for the anomalies described in this document. For example, to identify the silicon revision level using MPLAB IDE in conjunction with MPLAB ICD 3 or PICkit™ 3: 1.
PAGE 2
dsPIC33FJ12MC201/202 TABLE 2: SILICON ISSUE SUMMARY Module Feature Item Number Affected Revisions(1) Issue Summary A2 A3 A4 A5 JTAG Flash Programming 1. JTAG programming does not work. X X X X UART High-Speed Mode 2. UART receptions may be corrupted if the Baud Rate Generator (BRG) is set up for 4x mode. X X X X UART High-Speed Mode 3. The auto-baud feature may not calculate the correct baud rate when the BRG is set up for 4x mode. X X X X UART Auto-Baud 4.
PAGE 3
dsPIC33FJ12MC201/202 TABLE 2: SILICON ISSUE SUMMARY (CONTINUED) Module Feature Item Number Affected Revisions(1) Issue Summary A2 A3 A4 A5 I2C — 19. With the I2C module enabled, the port bits and external interrupt input functions (if any) associated with SCL and SDA pins do not reflect the actual digital logic levels on the pins. X X X X I2C 10-bit Addressing 20.
PAGE 4
dsPIC33FJ12MC201/202 Silicon Errata Issues Note: This document summarizes all silicon errata issues from all revisions of silicon, previous as well as current. Only the issues indicated by the shaded column in the following tables apply to the current silicon revision (A5). 1. Module: JTAG JTAG programming does not work. Work around None. 4. Module: UART With the auto-baud feature selected, the Sync Break character (0x55) may be loaded into the FIFO as data.
PAGE 5
dsPIC33FJ12MC201/202 7. Module: UART 10. Module: SPI When the UART is in 4x mode (BRGH = 1) and using two Stop bits (STSEL = 1), it may sample the first Stop bit instead of the second one. Setting the DISSCK bit in the SPIxCON1 register does not allow the user application to use the SCK pin as a General Purpose I/O pin. This issue does not affect the other UART configurations. Work around Work around None.
PAGE 6
dsPIC33FJ12MC201/202 13. Module: Product Identification Revision A2 devices marked as extended temperature range (E) devices only support industrial temperature range (I). Work around Use Revision A3 or newer devices marked as extended temperature range (E) devices. Affected Silicon Revisions A2 A3 A4 A5 X 14. Module: UART The UART error interrupt may not occur, or may occur at an incorrect time, if multiple errors occur during a short period of time.
PAGE 7
dsPIC33FJ12MC201/202 20. Module: I2C 22. Module: CPU In 10-bit Addressing mode, some address matches do not set the RBF flag or load the receive register, I2CxRCV, if the lower address byte matches the reserved addresses. In particular, these include all addresses with the form XX0000XXXX and XX1111XXXX, with the following exceptions: • • • • 001111000X 011111001X 101111010X 111111011X The EXCH instruction does not execute correctly.
PAGE 8
dsPIC33FJ12MC201/202 25. Module: QEI 26. Module: UART The Quadrature Encoder Interface (QEI) module does not generate an interrupt when MAXCNT is set to 0xFFFF and the following events occur: 1. POSCNT underflows from 0x0000 to 0xFFFF. 2. POSCNT stops. 3. POSCNT overflows from 0xFFFF to 0x0000. This sequence of events occurs when the motor is running in one direction, which causes POSCNT to underflow to 0xFFFF.
PAGE 9
dsPIC33FJ12MC201/202 27. Module: QEI 30. Module: ADC When the TQCS and TQGATE bits in the QEIxCON register are set, a QEI interrupt should be generated after an input pulse on the QEA input. This interrupt is not generated in the affected silicon. Work around None. If the ADC module is in an enabled state when the device enters Sleep mode as a result of executing a PWRSAV #0 instruction, the device power-down current (IPD) may exceed the specifications listed in the device data sheet.
PAGE 10
dsPIC33FJ12MC201/202 31. Module: CPU 33. Module: JTAG When using the Signed 32-by-16-bit Division instruction, div.sd, the overflow bit does not always get set when an overflow occurs. JTAG Flash programming is not supported. Work around None. Work around Test for and handle overflow conditions outside of the div.sd instruction. Affected Silicon Revisions A2 A3 A4 A5 X X X X Affected Silicon Revisions A2 A3 A4 A5 X X X X 32.
PAGE 11
dsPIC33FJ12MC201/202 Data Sheet Clarifications The following typographic corrections and clarifications are to be noted for the latest version of the device data sheet (DS70265E): Note: Corrections are shown in bold. Where possible, the original bold text formatting has been removed for clarity. 1. Module: Electrical Characteristics The maximum value for parameter DI19 (VIL specifications for SDAx and SCLx pins) was stated incorrectly in Table 24-9 of the current device data sheet.
PAGE 12
dsPIC33FJ12MC201/202 APPENDIX A: REVISION HISTORY Rev A Document (4/2009) Initial release of this document; issued for revision A2, A3 and A4 silicon. Includes silicon issues 1 (JTAG), 2-8 (UART), 9 (Interrupt Controller), 10 (SPI), 11-12 (I2C™), 13 (Product Identification), 14-15 (UART), 16 (Internal Voltage Regulator), 17 (PSV Operations), 18-21 (I2C), 22 (CPU), 23-24 (PWM) and 25 (QEI). This document replaces the following errata document: DS80328, “dsPIC33FJ12MC201/202 Rev.
PAGE 13
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
PAGE 14
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