Information
© 2010 Microchip Technology Inc. DS70152H-page 59
dsPIC33F/PIC24H PROGRAMMING SPECIFICATION
8.0 AC/DC CHARACTERISTICS
AND TIMING REQUIREMENTS
Table 8-1 lists the AC/DC characteristics and timing
requirements.
TABLE 8-1: AC/DC CHARACTERISTICS AND TIMING REQUIREMENTS
Standard Operating Conditions
Operating Temperature: –40ºC-85ºC. Programming at 25ºC is recommended.
Param
No.
Symbol Characteristic Min Max Units Conditions
D111 V
DD Supply Voltage During Programming 3.0 3.60 V Normal programming
(1)
D112 IPP Programming Current on MCLR —5μA—
D113 I
DDP Supply Current During Programming — 2 mA —
D031 V
IL Input Low Voltage VSS 0.2 VDD V—
D041 V
IH Input High Voltage 0.8 VDD VDD V—
D080 V
OL Output Low Voltage — 0.6 V IOL = 8.5 mA @ 3.6V
D090 V
OH Output High Voltage VDD – 0.7 — V IOH = -3.0 mA @ 3.6V
D012 C
IO Capacitive Loading on I/O pin (PGDx) — 50 pF To meet AC specifications
D013 CF Filter Capacitor Value on VCAP 110μF Required for controller core
P1 T
PGC Serial Clock (PGCx) Period (ICSP™) 200 — ns —
P1 T
PGCL Serial Clock (PGCx) Period (Enhanced
ICSP)
500 — ns —
P1A TPGCL Serial Clock (PGCx) Low Time (ICSP) 80 — ns —
P1A TPGCL Serial Clock (PGCx) Low Time (Enhanced
ICSP)
200 — ns —
P1B T
PGCH Serial Clock (PGCx) High Time (ICSP) 80 — ns —
P1B TPGCH Serial Clock (PGCx) High Time (Enhanced
ICSP)
200 — ns —
P2 T
SET1 Input Data Setup Time to Serial Clock ↓ 15 — ns —
P3 THLD1 Input Data Hold Time from PGCx ↓ 15 — ns —
P4 T
DLY1 Delay between 4-bit Command and
Command Operand
40 — ns —
P4A TDLY1A Delay between Command Operand and
Next 4-bit Command
40 — ns —
P5 T
DLY2 Delay between Last PGCx ↓ of Command
to First PGCx ↑ of Read of Data Word
20 — ns —
P6 T
SET2VDD ↑ Setup Time to MCLR ↑ 100 — ns —
P7 T
HLD2 Input Data Hold Time from MCLR ↑ 25 — ms —
P8 T
DLY3 Delay between Last PGCx ↓ of Command
Byte to PGDx ↑ by Programming
Executive
12 — μs—
P9a TDLY4 Programming Executive Command
Processing Time
10 — μs—
Note 1: VDD must also be supplied to the AVDD pins during programming. AVDD and AVSS should always be within
±0.3V of VDD and VSS, respectively.
2: Time depends on the FRC accuracy and the value of the FRC Oscillator tuning register. Refer to
“Electrical Characteristics” section in the specific device data sheet.