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dsPIC33F/PIC24H PROGRAMMING SPECIFICATION
DS70152H-page 48 © 2010 Microchip Technology Inc.
5.10 Verify Code Memory and
Configuration Word
The verify step involves reading back the code memory
space and comparing it against the copy held in the
programmer’s buffer. The Configuration registers are
verified with the rest of the code.
The verify process is illustrated in Figure 5-9. Memory
reads occur a single byte at a time, so two bytes must
be read to compare against the word in the program-
mer’s buffer. Refer to Section 5.8 “Reading Code
Memory” for implementation details of reading code
memory.
FIGURE 5-9: VERIFY CODE
MEMORY FLOW
5.11 Reading the Application ID Word
The Application ID Word is stored at address 0x8007F0
in executive code memory. To read this memory
location, you must use the SIX control code to move
this program memory location to the VISI register.
Then, the REGOUT control code must be used to clock
the contents of the VISI register out of the device. The
corresponding control and instruction codes that must
be serially transmitted to the device to perform this
operation are shown in Table 5-10.
After the programmer has clocked out the Application
ID Word, it must be inspected. If the application ID has
the value 0xCB, the programming executive is resident
in memory and the device can be programmed using
the mechanism described in Section 3.0 “Device
Programming – Enhanced ICSP”. However, if the
application ID has any other value, the programming
executive is not resident in memory; it must be loaded
to memory before the device can be programmed. The
procedure for loading the programming executive to
memory is described in Section 6.0 “Programming
the Programming Executive to Memory”.
5.12 Exiting ICSP Mode
Exiting Program/Verify mode is done by removing VIH
from MCLR, as illustrated in Figure 5-10. The only
requirement for exit is that an interval P16 should
elapse between the last clock and program signals on
PGCx and PGDx before removing V
IH.
FIGURE 5-10: EXITING ICSP™ MODE
Note: Because the Configuration registers
include the device code protection bit,
code memory should be verified
immediately after writing, if the code
protection is enabled. This is because the
device will not be readable or verifiable if
a device Reset occurs after the code-pro-
tect bit in the FGS Configuration register
has been cleared.
Read Low Byte
Read High Byte
Does
Word = Expect
Data?
All
code memory
verified?
No
Yes
No
Set TBLPTR = 0
Start
Yes
End
with Post-Increment
with Post-Increment
Failure
Report Error
MCLR
P16
PGDx
PGDx = Input
PGCx
VDD
VIH
VIH
P17