Information

dsPIC33F/PIC24H PROGRAMMING SPECIFICATION
DS70152H-page 16 © 2010 Microchip Technology Inc.
TABLE 3-4: dsPIC33FJ12GP201/202 AND PIC24HJ12GP201/201 DEVICE CONFIGURATION
REGISTER MAP
TABLE 3-3: dsPIC33FJ06GS101/X02 AND dsPIC33FJ16GSX02/X04 DEVICE CONFIGURATION
REGISTER MAP
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0xF80000 FBS — — — — BSS<2:0> BWRP
0xF80002 Reserved
— — — — — — — —
0xF80004 FGS
— — — — —GSS<1:0>GWRP
0xF80006 FOSCSEL IESO
— — — —FNOSC<2:0>
0xF80008 FOSC FCKSM<1:0> IOL1WAY
— — OSCIOFNC POSCMD<1:0>
0xF8000A FWDT FWDTEN WINDIS — WDTPRE WDTPOST<3:0>
0xF8000C FPOR
— — — — Reserved
(2)
FPWRT<2:0>
0xF8000E FICD Reserved
(1)
JTAGEN
(3)
— — —ICS<1:0>
0xF80010 FUID0 User Unit ID Byte 0
0xF80012 FUID1 User Unit ID Byte 1
Legend: — = unimplemented bit, read as ‘0’.
Note 1: These bits are reserved (read as ‘1’) and must be programmed as ‘1’.
2: This bit reads the current programmed value.
3: The JTAGEN bit is set to ‘1’ by factory default. Microchip programmers such as MPLAB
®
ICD 2 and REAL
ICE™ in-circuit emulator clear this bit by default when connecting to a device.
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0xF80000 FBS
— — — — BSS<2:0> BWRP
0xF80002 Reserved Reserved
(1)
0xF80004 FGS — — — — — GSS<1:0> GWRP
0xF80006 FOSCSEL IESO
— — — —FNOSC<2:0>
0xF80008 FOSC FCKSM<1:0> IOL1WAY — — OSCIOFNC POSCMD<1:0>
0xF8000A FWDT FWDTEN WINDIS
— WDTPRE WDTPOST<3:0>
0xF8000C FPOR
— — —ALTI2C—FPWRT<2:0>
0xF8000E FICD Reserved
(1)
JTAGEN
(2)
— — —ICS<1:0>
0xF80010 FUID0 User Unit ID Byte 0
0xF80012 FUID1 User Unit ID Byte 1
0xF80014 FUID2 User Unit ID Byte 2
0xF80016 FUID3 User Unit ID Byte 3
Legend: — = unimplemented bit, read as ‘0’.
Note 1: These reserved bits read as ‘1’ and must be programmed as ‘1’.
2: The JTAGEN bit is set to ‘1’ by factory default. Microchip programmers such as MPLAB ICD 2 and REAL
ICE in-circuit emulator clear this bit by default when connecting to a device.