Datasheet

dsPIC33FJ12MC201/202
DS70265E-page 290 © 2007-2011 Microchip Technology Inc.
Section 17.0 “Inter-Integrated
Circuit™ (I
2
C™)”
Removed the following sections, which are now available in the related section
of the dsPIC33F Family Reference Manual:
• 17.3 “I
2
C Interrupts”
• 17.4 “Baud Rate Generator” (retained Figure 17-1: I
2
C Block Diagram)
• 17.5 “I
2
C Module Addresses
• 17.6 “Slave Address Masking”
• 17.7 “IPMI Support”
• 17.8 “General Call Address Support”
• 17.9 “Automatic Clock Stretch”
• 17.10 “Software Controlled Clock Stretching (STREN = 1)”
• 17.11 “Slope Control”
• 17.12 “Clock Arbitration”
• 17.13 “Multi-Master Communication, Bus Collision, and Bus Arbitration
• 17.14 “Peripheral Pin Select Limitations
Section 18.0 “Universal
Asynchronous Receiver
Transmitter (UART)”
Removed the following sections, which are now available in the related section
of the dsPIC33F Family Reference Manual:
• 18.1 “UART Baud Rate Generator”
• 18.2 “Transmitting in 8-bit Data Mode
• 18.3 “Transmitting in 9-bit Data Mode
• 18.4 “Break and Sync Transmit Sequence”
• 18.5 “Receiving in 8-bit or 9-bit Data Mode”
• 18.6 “Flow Control Using UxCTS
and UxRTS Pins”
• 18.7 “Infrared Support”
Removed IrDA references and Note 1, and updated the bit and bit value
descriptions for UTXINV (UxSTA<14>) in the UARTx Status and Control
Register (see Register 18-2).
TABLE 25-1: MAJOR SECTION UPDATES
Section Name Update Description