Datasheet

dsPIC33FJ12MC201/202
DS70265E-page 194 © 2007-2011 Microchip Technology Inc.
FIGURE 20-1: ADC1 BLOCK DIAGRAM FOR dsPIC33FJ12MC201 DEVICES
SAR ADC
S/H0
S/H1
ADC1BUF0
ADC1BUF1
ADC1BUF2
ADC1BUFF
ADC1BUFE
AN0
AN7
AN1
VREFL
CH0SB<4:0>
CH0NA
CH0NB
+
-
AN0
AN3
CH123SA
CH123SB
CH123NA
CH123NB
AN6
+
-
S/H2
AN1
CH123SA
CH123SB
CH123NA
CH123NB
AN7
+
-
S/H3
AN2
CH123SA CH123SB
CH123NA
CH123NB
+
-
CH1
(2)
CH0
CH2
(2)
CH3
(2)
CH0SA<4:0>
Channel
Scan
CSCNA
Alternate
V
REF+
(1)
AVDD
AVSS
VREF-
(1)
Note 1: VREF+, VREF- inputs can be multiplexed with other analog inputs.
2: Channels 1, 2, and 3 are not applicable for the 12-bit mode of operation.
Input Selection
V
REFH
VREFL
VREFL
VREFL
VREFL