Datasheet

dsPIC33FJ12MC201/202
DS70265E-page 294 © 2007-2011 Microchip Technology Inc.
Revision E (July 2011)
This revision includes formatting changes and minor
typographical throughout the data sheet text.
Global changes include:
• Removed Preliminary marking from the footer
• Updated all family reference manual information
in the note boxes located at the beginning of most
chapters
• Changed all instances of V
CAP/VDDCORE to VCAP
All other major changes are referenced by their
respective section in the following table.
TABLE 25-3: MAJOR SECTION UPDATES
Section Name Update Description
Section 2.0 “Guidelines for Getting
Started with 16-bit Digital Signal
Controllers”
Changed the title of section 2.3 to Section 2.3 “CPU Logic Filter
Capacitor Connection (VCAP)”.
Updated the second paragraph in Section 2.9 “Unused I/Os”.
Section 4.0 “Memory Organization” Revised the data memory implementation value in the third paragraph
of Section 4.2 “Data Address Space”.
Updated the All Resets values for TMR1, TMR2, and TMR3 in the
Timer Register Map (see Tab le 4 -5 ).
Section 8.0 “Oscillator Configuration” Added Note 3 to the Oscillator Control Register (see Register 8-1).
Added Note 2 to the Clock Divisor Register (see Register 8-2).
Added Note 1 to the PLL Feedback Divisor Register (see Register 8-3).
Added Note 2 to the FRC Oscillator Tuning Register (see Register 8-4).
Section 10.0 “I/O Ports” Revised the second paragraph in Section 10.1.1 “Open-Drain
Configuration”.
Section 14.0 “Output Compare” Updated the Output Compare Module Block Diagram (see Figure 14-1).
Section 19.0 “Universal Asynchronous
Receiver Transmitter (UART)”
Revised the UART module Baud Rate features, replacing both items
with “Baud rates ranging from 10 Mbps to 38 bps at 40 MIPS”.
Section 21.0 “Special Features” Revised all paragraphs in Section 21.1 “Configuration Bits”.
Updated the Device Configuration Register Map (see Table 21-1).
Added the RTSP Effect column in the Configuration Bits Description
(see Table 21-2).