Datasheet

© 2007-2011 Microchip Technology Inc. DS70265E-page 37
dsPIC33FJ12MC201/202
XMODSRT 0048 XS<15:1> 0xxxx
XMODEND 004A XE<15:1> 1xxxx
YMODSRT 004C YS<15:1> 0xxxx
YMODEND 004E YE<15:1> 1xxxx
XBREV 0050 BREN XB<14:0> xxxx
DISICNT 0052 — — Disable Interrupts Counter Register xxxx
TABLE 4-1: CPU CORE REGISTERS MAP (CONTINUED)
SFR Name
SFR
Addr
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
All
Resets
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-2: CHANGE NOTIFICATION REGISTER MAP FOR dsPIC33FJ12MC202
SFR
Name
SFR
Addr
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
All
Resets
CNEN1
0060 CN15IE CN14IE CN13IE CN12IE CN11IE — — — CN7IE CN6IE CN5IE CN4IE CN3IE CN2IE CN1IE CN0IE 0000
CNEN2 0062 — CN30IE CN29IE — CN27IE — — CN24IE CN23IE CN22IE CN21IE — — — — CN16IE 0000
CNPU1 0068 CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE — — — CN7PUE CN6PUE CN5PUE CN4PUE CN3PUE CN2PUE CN1PUE CN0PUE 0000
CNPU2 006A — CN30PUE CN29PUE — CN27PUE — — CN24PUE CN23PUE CN22PUE CN21PUE — — — — CN16PUE 0000
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-3: CHANGE NOTIFICATION REGISTER MAP FOR dsPIC33FJ12MC201
SFR
Name
SFR
Addr
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
All
Resets
CNEN1
0060
—
CN14IE CN13IE CN12IE CN11IE
— — — — —
CN5IE CN4IE CN3IE CN2IE CN1IE CN0IE
0000
CNEN2
00C2
—
CN30IE CN29IE
— — — — —
CN23IE CN22IE CN21IE
— — — — —
0000
CNPU1
0068
—
CN14PUE CN13PUE CN12PUE CN11PUE
— — — — —
CN5PUE CN4PUE CN3PUE CN2PUE CN1PUE CN0PUE
0000
CNPU2
006A
—
CN30PUE CN29PUE
— — — — —
CN23PUE CN22PUE CN21PUE
— — — — —
0000
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.