Datasheet

© 2007-2011 Microchip Technology Inc. DS70264E-page 99
dsPIC33FJ12GP201/202
For a primary oscillator or FRC oscillator, output ‘FIN’,
the PLL output ‘FOSC’ is given by Equation 8-2.
EQUATION 8-2: FOSC CALCULATION
For example, suppose a 10 MHz crystal is being used,
with “XT with PLL” being the selected oscillator mode.
• If PLLPRE<4:0> = 0, then N1 = 2. This yields a
VCO input of 10/2 = 5 MHz, which is within the
acceptable range of 0.8-8 MHz.
• If PLLDIV<8:0> = 0x1E, then M = 32. This yields a
VCO output of 5 x 32 = 160 MHz, which is within
the 100-200 MHz ranged needed.
• If PLLPOST<1:0> = 0, then N2 = 2. This provides
a Fosc of 160/2 = 80 MHz. The resultant device
operating speed is 80/2 = 40 MIPS.
EQUATION 8-3: XT WITH PLL MODE
EXAMPLE
FIGURE 8-2: dsPIC33FJ12GP201/202 PLL BLOCK DIAGRAM
FOSC FIN
M
N1 N2⋅
----------------------
⎝⎠
⎛⎞
⋅=
FCY
FOSC
2
-------------
1
2
---
10000000 32⋅
22⋅
-------------------------------------
⎝⎠
⎛⎞
40 MIPS== =
0.8-8.0 MHz
Here
(1)
100-200 MHz
Here
(1)
Divide by
2, 4, 8
Divide by
2-513
Divide by
2-33
Source (Crystal, External Clock
PLLPRE
X
VCO
PLLDIV
PLLPOST
or Internal RC)
12.5-80 MHz
Here
(1)
FOSC
Note 1: This frequency range must be satisfied at all times.
FVCO
N1
M
N2