Datasheet

dsPIC33FJ12GP201/202
DS70264E-page 68 © 2007-2011 Microchip Technology Inc.
6.9.0.2 UNINITIALIZED W REGISTER
RESET
Any attempts to use the uninitialized W register as an
address pointer will Reset the device. The W register
array (with the exception of W15) is cleared during all
Resets and is considered uninitialized until written to.
6.9.0.3 SECURITY RESET
If a Program Flow Change (PFC) or Vector Flow
Change (VFC) targets a restricted location in a
protected segment (Boot and Secure Segment), that
operation will cause a security Reset.
The PFC occurs when the Program Counter is
reloaded as a result of a Call, Jump, Computed Jump,
Return, Return from Subroutine, or other form of
branch instruction.
The VFC occurs when the Program Counter is
reloaded with an Interrupt or Trap vector.
Refer to Section 19.8 “Code Protection and
CodeGuard™ Security” for more information on
Security Reset.
6.10 Using the RCON Status Bits
The user application can read the Reset Control regis-
ter (RCON) after any device Reset to determine the
cause of the Reset.
Table 6-3 provides a summary of Reset Flag Bit
operation.
TABLE 6-3: RESET FLAG BIT OPERATION
Note: The status bits in the RCON register
should be cleared after they are read so
that the next RCON register value after a
device Reset will be meaningful.
Flag Bit Set by: Cleared by:
TRAPR (RCON<15>) Trap conflict event POR, BOR
IOPWR (RCON<14>) Illegal opcode, or uninitialized W register
access, or Security Reset
POR, BOR
CM (RCON<9>)
Configuration Mismatch POR, BOR
EXTR (RCON<7>) MCLR Reset POR
SWR (RCON<6>) RESET instruction POR, BOR
WDTO (RCON<4>) WDT Time-out PWRSAV instruction,
CLRWDT instruction, POR, BOR
SLEEP (RCON<3>) PWRSAV #SLEEP instruction POR, BOR
IDLE (RCON<2>) PWRSAV #IDLE instruction POR, BOR
BOR (RCON<1>) POR, BOR
POR (RCON<0>) POR
Note: All Reset flag bits can be set or cleared by user software.