Datasheet

dsPIC33FJ12GP201/202
DS70264E-page 66 © 2007-2011 Microchip Technology Inc.
6.2 POR
A POR circuit ensures the device is reset from power-
on. The POR circuit is active until V
DD crosses the
VPOR threshold and the delay TPOR has elapsed. The
delay TPOR ensures the internal device bias circuits
become stable.
The device supply voltage characteristics must meet
the specified starting voltage and rise rate
requirements to generate the POR. Refer to
Section 22.0 “Electrical Characteristics” for details.
The POR status bit (POR) in the Reset Control register
(RCON<0>) is set to indicate the POR.
6.3 BOR and PWRT
The on-chip regulator has a BOR circuit that resets the
device when the V
DD is too low (VDD < VBOR) for proper
device operation. The BOR circuit keeps the device in
Reset until VDD crosses VBOR threshold and the delay
T
BOR has elapsed. The delay TBOR ensures the voltage
regulator output becomes stable.
The BOR status bit (BOR) in the Reset Control register
(RCON<1>) is set to indicate the BOR.
The device will not run at full speed after a BOR as the
V
DD should rise to acceptable levels for full-speed
operation. The PWRT provides power-up time delay
(T
PWRT) to ensure that the system power supplies have
stabilized at the appropriate levels for full-speed
operation before the SYSRST
is released.
The power-up timer delay (T
PWRT) is programmed by
the Power-on Reset Timer Value Select bits
(FPWRT<2:0>) in the POR Configuration register
(FPOR<2:0>), which provides eight settings (from 0 ms
to 128 ms). Refer to Section 19.0 “Special Features”
for further details.
Figure 6-3 shows the typical brown-out scenarios. The
Reset delay (T
BOR + TPWRT) is initiated each time VDD
rises above the VBOR trip point.
FIGURE 6-3: BROWN-OUT SITUATIONS
VDD
SYSRST
VBOR
V
DD
SYSRST
VBOR
V
DD
SYSRST
VBOR
T
BOR + TPWRT
VDD dips before PWRT expires
T
BOR + TPWRT
TBOR + TPWRT