Datasheet
dsPIC33FJ12GP201/202
DS70264E-page 56 © 2007-2011 Microchip Technology Inc.
5.2 RTSP Operation
The dsPIC33FJ12GP201/202 Flash program memory
array is organized into rows of 64 instructions or 192
bytes. RTSP allows the user application to erase a
page of memory, which consists of eight rows (512
instructions), and to program one row or one word. The
8-row erase pages and single row write rows are edge-
aligned from the beginning of program memory, on
boundaries of 1536 bytes and 192 bytes, respectively.
The program memory implements holding buffers that
can contain 64 instructions of programming data. Prior
to the actual programming operation, the write data
must be loaded into the buffers sequentially. The
instruction words loaded must always be from a group
of 64 boundary.
The basic sequence for RTSP programming is to set up
a Table Pointer, and then perform a series of TBLWT
instructions to load the buffers. Programming is per-
formed by setting the control bits in the NVMCON reg-
ister. A total of 64 TBLWTL and TBLWTH instructions
are required to load the instructions.
All of the table write operations are single-word writes
(two instruction cycles) because only the buffers are
written. A programming cycle is required for
programming each row.
5.3 Programming Operations
A complete programming sequence is necessary for
programming or erasing the internal Flash in RTSP
mode. The processor stalls (waits) until the
programming operation is finished.
The programming time depends on the FRC accuracy
(see Table 22-18) and the value of the FRC Oscillator
Tuning register (see Register 8-4). Use the following
formula to calculate the minimum and maximum values
for the Row Write Time, Page Erase Time, and Word
Write Cycle Time parameters (see Table 22-12).
EQUATION 5-1: PROGRAMMING TIME
For example, if the device is operating at +125°C, the
FRC accuracy will be ±5%. If the TUN<5:0> bits (see
Register 8-4) are set to ‘b111111, the minimum row
write time is equal to Equation 5-2.
EQUATION 5-2: MINIMUM ROW WRITE
TIME
The maximum row write time is equal to Equation 5-3.
EQUATION 5-3: MAXIMUM ROW WRITE
TIME
Setting the WR bit (NVMCON<15>) starts the opera-
tion, and the WR bit is automatically cleared when the
operation is finished.
5.4 Control Registers
Two SFRs are used to read and write the program
Flash memory:
• NVMCON: Flash Memory Control Register
• NVMKEY: Nonvolatile Memory Key Register
The NVMCON register (Register 5-1) controls which
blocks are to be erased, which memory type is to be
programmed, and the start of the programming cycle.
NVMKEY (Register 5-2) is a write-only register that is
used for write protection. To start a programming or
erase sequence, the user application must consecu-
tively write 0x55 and 0xAA to the NVMKEY register.
Refer to Section 5.3 “Programming Operations” for
further details.
T
7.37 MHz FRC Accuracy()% FRC Tuning()%××
----------------------------------------------------------------------------------------------------------------------------
T
RW
11064 Cycles
7.37 MHz 10.05+()1 0.00375–()××
------------------------------------------------------------------------------------------------
1.435ms==
T
RW
11064 Cycles
7.37 MHz 10.05–()1 0.00375–()××
------------------------------------------------------------------------------------------------
1.586ms==