Datasheet
dsPIC33FJ12GP201/202
DS70264E-page 254 © 2007-2011 Microchip Technology Inc.
Fundamental Modes Supported.................................. 46
MAC Instructions......................................................... 46
MCU Instructions ........................................................ 45
Move and Accumulator Instructions............................ 46
Other Instructions........................................................ 46
Instruction Set
Overview ................................................................... 184
Summary................................................................... 181
Instruction-Based Power-Saving Modes ........................... 107
Idle ............................................................................ 108
Sleep......................................................................... 107
Internal RC Oscillator
Use with WDT ........................................................... 179
Internet Address................................................................ 257
Interrupt Control and Status Registers................................ 73
IECx ............................................................................ 73
IFSx............................................................................. 73
INTCON1 .................................................................... 73
INTCON2 .................................................................... 73
IPCx ............................................................................ 73
Interrupt Setup Procedures ................................................. 95
Initialization ................................................................. 95
Interrupt Disable.......................................................... 95
Interrupt Service Routine ............................................ 95
Trap Service Routine .................................................. 95
Interrupt Vector Table (IVT) ................................................ 69
Interrupts Coincident with Power Save Instructions.......... 108
J
JTAG Boundary Scan Interface ........................................ 175
M
Memory Organization.......................................................... 31
Microchip Internet Web Site .............................................. 257
Modulo Addressing ............................................................. 47
Applicability ................................................................. 48
Operation Example ..................................................... 47
Start and End Address................................................ 47
W Address Register Selection .................................... 47
MPLAB ASM30 Assembler, Linker, Librarian ................... 190
MPLAB Integrated Development Environment Software .. 189
MPLAB PM3 Device Programmer..................................... 192
MPLAB REAL ICE In-Circuit Emulator System................. 191
MPLINK Object Linker/MPLIB Object Librarian ................ 190
N
NVM Module
Register Map............................................................... 44
O
Open-Drain Configuration ................................................. 112
Output Compare................................................................ 139
Registers................................................................... 141
P
Packaging ......................................................................... 237
Details ....................................................................... 239
Marking ............................................................. 237, 238
Peripheral Module Disable (PMD)..................................... 108
Peripheral Pin Select
Input Register Map...................................................... 40
Pinout I/O Descriptions (table) ............................................ 11
PMD Module
Register Map............................................................... 44
PORTA
Register Map............................................................... 43
PORTB
Register Map .............................................................. 43
Power-on Reset (POR)....................................................... 66
Power-Saving Features .................................................... 107
Clock Frequency and Switching ............................... 107
Program Address Space..................................................... 31
Construction ............................................................... 50
Data Access from Program Memory Using Program
Space Visibility ................................................... 53
Data Access from Program Memory Using Table Instruc-
tions .................................................................... 52
Data Access from, Address Generation ..................... 51
Memory Map............................................................... 31
Table Read Instructions
TBLRDH ............................................................. 52
TBLRDL.............................................................. 52
Visibility Operation ...................................................... 53
Program Memory
Interrupt Vector........................................................... 32
Organization ............................................................... 32
Reset Vector............................................................... 32
R
Reader Response............................................................. 258
Registers
AD1CHS0 (ADC1 Input Channel 0 Select ................ 173
AD1CHS123 (ADC1 Input Channel 1, 2, 3 Select)... 171
AD1CON1 (ADC1 Control 1) .................................... 167
AD1CON2 (ADC1 Control 2) .................................... 169
AD1CON3 (ADC1 Control 3) .................................... 170
AD1CSSL (ADC1 Input Scan Select Low)................ 174
AD1PCFGL (ADC1 Port Configuration Low) ............ 174
CLKDIV (Clock Divisor) ............................................ 103
CORCON (Core Control) ...................................... 24, 74
I2CxCON (I2Cx Control) ........................................... 151
I2CxMSK (I2Cx Slave Mode Address Mask) ............ 155
I2CxSTAT (I2Cx Status) ........................................... 153
ICxCON (Input Capture x Control)............................ 138
IEC0 (Interrupt Enable Control 0) ............................... 82
IEC1 (Interrupt Enable Control 0) ............................... 84
IEC4 (Interrupt Enable Control 0) ............................... 85
IFS0 (Interrupt Flag Status 0) ..................................... 78
IFS1 (Interrupt Flag Status 1) ..................................... 80
IFS4 (Interrupt Flag Status 4) ..................................... 81
INTCON1 (Interrupt Control 1).................................... 75
INTCON2 (Interrupt Control 2).................................... 77
INTTREG Interrupt Control and Status Register ........ 94
IPC0 (Interrupt Priority Control 0) ............................... 86
IPC1 (Interrupt Priority Control 1) ............................... 87
IPC16 (Interrupt Priority Control 16) ........................... 93
IPC2 (Interrupt Priority Control 2) ............................... 88
IPC3 (Interrupt Priority Control 3) ............................... 89
IPC4 (Interrupt Priority Control 4) ............................... 90
IPC5 (Interrupt Priority Control 5) ............................... 91
IPC7 (Interrupt Priority Control 7) ............................... 92
NVMCON (Flash Memory Control) ............................. 57
NVMCON (Nonvolatile Memory Key) ......................... 58
OCxCON (Output Compare x Control) ..................... 141
OSCCON (Oscillator Control) ................................... 101
OSCTUN (FRC Oscillator Tuning)............................ 105
PLLFBD (PLL Feedback Divisor).............................. 104
PMD1 (Peripheral Module Disable Control Register 1) ..
109
PMD2 (Peripheral Module Disable Control Register 2) ..
110
RCON (Reset Control)................................................ 62