Datasheet

© 2007-2011 Microchip Technology Inc. DS70264E-page 115
dsPIC33FJ12GP201/202
TABLE 10-2: OUTPUT SELECTION FOR REMAPPABLE PIN (RPn)
10.4.3 CONTROLLING CONFIGURATION
CHANGES
Because peripheral remapping can be changed during
run time, some restrictions on peripheral remapping
are needed to prevent accidental configuration
changes. dsPIC33FJ12GP201/202 devices include
three features to prevent alterations to the peripheral
map:
• Control register lock sequence
• Continuous state monitoring
• Configuration bit pin select lock
10.4.3.1 Control Register Lock
Under normal operation, writes to the RPINRx and
RPORx registers are not allowed. Attempted writes
appear to execute normally, but the contents of the
registers remain unchanged. To change these
registers, they must be unlocked in hardware. The
register lock is controlled by the IOLOCK bit
(OSCCON<6>). Setting the IOLOCK bit prevents
writes to the control registers; clearing the IOLOCK bit
allows writes.
To set or clear the IOLOCK bit, a specific command
sequence must be executed:
1. Write 0x46 to OSCCON<7:0>.
2. Write 0x57 to OSCCON<7:0>.
3. Clear (or set) the IOLOCK bit as a single
operation.
Unlike the similar sequence with the oscillator’s LOCK
bit, IOLOCK remains in one state until changed. This
allows all of the peripheral pin selects to be configured
with a single unlock sequence followed by an update to
all control registers, then locked with a second lock
sequence.
10.4.3.2 Continuous State Monitoring
In addition to being protected from direct writes, the
contents of the RPINRx and RPORx registers are
constantly monitored in hardware by shadow registers.
If an unexpected change in any of the registers occurs
(such as cell disturbances caused by ESD or other
external events), a configuration mismatch Reset will
be triggered.
10.4.3.3 Configuration Bit Pin Select Lock
As an additional level of safety, the device can be con-
figured to prevent more than one write session to the
RPINRx and RPORx registers. The IOL1WAY
(FOSC<5>) configuration bit blocks the IOLOCK bit
from being cleared after it has been set once.
In the default (unprogrammed) state, the IOL1WAY bit
is set, restricting users to one write session. Program-
ming IOL1WAY allows user applications unlimited
access (with the proper use of the unlock sequence) to
the peripheral pin select registers.
10.5 Peripheral Pin Select Registers
The dsPIC33FJ12GP201/202 devices implement 17
registers for remappable peripheral configuration:
• Input Remappable Peripheral Registers (9)
• Output Remappable Peripheral Registers (8)
Function RPnR<4:0> Output Name
NULL 00000 RPn tied to default port pin
U1TX 00011 RPn tied to UART1 Transmit
U1RTS
00100 RPn tied to UART1 Ready To Send
SDO1 00111 RPn tied to SPI1 Data Output
SCK1OUT 01000 RPn tied to SPI1 Clock Output
SS1OUT 01001 RPn tied to SPI1 Slave Select Output
OC1 10010 RPn tied to Output Compare 1
OC2 10011 RPn tied to Output Compare 2
Note: MPLAB
®
C30 provides built-in C
language functions for unlocking the
OSCCON register:
__builtin_write_OSCCONL(value)
__builtin_write_OSCCONH(value)
See the MPLAB IDE help files for more
information.
Note: Input and Output register values can only
be changed if the IOLOCK bit
(OSCCON<6>) = 0. See Section 10.4.3.1
“Control Register Lock” for a specific
command sequence.