Datasheet

© 2007-2012 Microchip Technology Inc. DS70291G-page 133
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04 AND dsPIC33FJ128MCX02/X04
8.1 DMA Resources
Many useful resources related to DMA are provided on
the main product page of the Microchip web site for the
devices listed in this data sheet. This product page,
which can be accessed using this link, contains the
latest updates and additional information.
8.1.1 KEY RESOURCES
Section 38. “Direct Memory Access (Part III)”
(DS70215)
Code Samples
Application Notes
Software Libraries
Webinars
All related dsPIC33F/PIC24H Family Reference
Manuals Sections
Development Tools
8.2 DMAC Registers
Each DMAC Channel x (x = 0, 1, 2, 3, 4, 5, 6 or 7)
contains the following registers:
A 16-bit DMA Channel Control register
(DMAxCON)
A 16-bit DMA Channel IRQ Select register
(DMAxREQ)
A 16-bit DMA RAM Primary Start Address register
(DMAxSTA)
A 16-bit DMA RAM Secondary Start Address
register (DMAxSTB)
A 16-bit DMA Peripheral Address register
(DMAxPAD)
A 10-bit DMA Transfer Count register (DMAxCNT)
An additional pair of status registers, DMACS0 and
DMACS1, are common to all DMAC channels.
DMACS0 contains the DMA RAM and SFR write
collision flags, XWCOLx and PWCOLx, respectively.
DMACS1 indicates DMA channel and Ping-Pong mode
status.
The DMAxCON, DMAxREQ, DMAxPAD and
DMAxCNT are all conventional read/write registers.
Reads of DMAxSTA or DMAxSTB reads the contents
of the DMA RAM Address register. Writes to
DMAxSTA or DMAxSTB write to the registers. This
allows the user to determine the DMA buffer pointer
value (address) at any time.
The interrupt flags (DMAxIF) are located in an IFSx
register in the interrupt controller. The corresponding
interrupt enable control bits (DMAxIE) are located in
an IECx register in the interrupt controller, and the
corresponding interrupt priority control bits (DMAxIP)
are located in an IPCx register in the interrupt
controller.
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