Information

 2009-2013 Microchip Technology Inc. DS80442J-page 9
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04 and dsPIC33FJ128MCX02/X04
22. Module: UART
The UARTx module will not generate consecutive
Break characters. Trying to perform a back-to-
back Break character transmission will cause the
UARTx module to transmit the dummy character,
used to generate the first Break character, instead
of transmitting the second Break character. Break
characters are generated correctly if they are
followed by a non-Break character transmission.
Work around
None.
Affected Silicon Revisions
23. Module: QEI
When the TQCS and TQGATE bits in the
QEIxCON register are set, a QEI interrupt should
be generated after an input pulse on the QEA
input. This interrupt is not generated in the affected
silicon.
Work around
None.
Affected Silicon Revisions
24. Module: QEI
When the TQCS and TQGATE bits in the
QEIxCON register are set, the POSxCNT counter
should not increment but erroneously does, and if
allowed to increment to match MAXxCNT, a QEI
interrupt will be generated.
Work around
To prevent the erroneous increment of POSxCNT
while running the QEI in Timer Gated
Accumulation mode, initialize MAXxCNT = 0.
Affected Silicon Revisions
25. Module: Audio DAC
The audio DAC positive differential output
voltage and negative differential output voltage
(Parameters DA01 and DA02, respectively) may
not meet the specifications listed in the data sheet.
Work around
None.
Affected Silicon Revisions
A1 A2 A3 A4 A5
XXXX
X
A1 A2 A3 A4 A5
XXXX
X
A1 A2 A3 A4 A5
XXXX
X
A1 A2 A3 A4
A5
XXX