Information

dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04 and dsPIC33FJ128MCX02/X04
DS80442J-page 4  2009-2013 Microchip Technology Inc.
ECAN™ Receive
Operation
17. The ECAN™ module may not store the received data in
the correct location.
XXX
CPU EXCH
Instruction
18. The EXCH instruction does not execute correctly. X X X X X
PWM Debug Mode 19. PTMR does not keep counting down after halting code
execution in Debug mode.
XXXXX
PWM Doze Mode 20. The Motor Control PWM module generates more
interrupts than expected when Doze mode is used and
the output postscaler value is different than 1:1.
XXXXX
SPI Transmit
Operation
21. Writing to the SPIxBUF register as soon as the TBF bit
is cleared will cause SPIx module to ignore written data.
XXXXX
UART Break
Character
Generation
22. The UART module will not generate back-to-back Break
characters.
XXXXX
QEI Timer Gated
Accumulation
Mode
23. When Timer Gated Accumulation mode is enabled, the
QEI does not generate an interrupt on every falling
edge.
XXXXX
QEI Timer Gated
Accumulation
Mode
24. When Timer Gated Accumulation mode is enabled, and
an external signal is applied, the POSxCNT increments
and generates an interrupt after a match with MAXxCNT.
XXXXX
Audio DAC Voltage
Specifications
25. The audio DAC positive and negative output differential
voltages may not meet the specifications listed in the
data sheet.
XXX
ADC Current
Consumption
in Sleep
Mode
26. If the ADC module is in an enabled state when the
device enters Sleep mode, the Power-Down (I
PD)
current of the device may exceed the device data sheet
specifications.
XXXXX
JTAG Boundary
Scan
27. On 28-pin devices, boundary scan does not function
correctly for Pin 7.
XXXXX
RTCC Operation
During Reset
28. The RTCC module gets reset on any device Reset,
instead of getting reset only on a POR or BOR.
XXXXX
All +150°C
Operation
29. These revisions of silicon only support +140°C
operation instead of +150°C for high-temperature
operating temperature.
XXX
I/O Port Data Direction
Setting
30. When the RB8 pin is in open-drain configuration, the
data direction depends upon the TRISB9 bit instead of
the TRISB8 bit.
XXXXX
CPU Interrupt
Disable
31. When a previous DISI instruction is active (i.e., the
DISICNT register is non-zero), and the value of the
DISICNT register is updated manually, the DISICNT
register freezes and disables interrupts permanently.
XXXXX
CPU div.sd 32. When using the div.sd instruction, the overflow bit is
not getting set when an overflow occurs.
XXXXX
UART TX Interrupt 33. A Transmit (TX) interrupt may occur before the data
transmission is complete.
XXXXX
JTAG Flash
Programming
34. JTAG Flash programming is not supported. X X X X X
TABLE 2: SILICON ISSUE SUMMARY (CONTINUED)
Module Feature
Item
Number
Issue Summary
Affected
Revisions
(1)
A1 A2 A3 A4 A5
Note 1: Only those issues indicated in the last column apply to the current silicon revision.