Information

2009-2013 Microchip Technology Inc. DS80442J-page 11
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04 and dsPIC33FJ128MCX02/X04
29. Module: All
The affected silicon revisions listed below are not
warranted for operation at +150°C.
Work around
Only use the affected revisions of silicon for the
high-temperature operating range from -40°C to
+140°C.
Affected Silicon Revisions
30. Module: I/O Port
When the ODCB8 bit is set to ‘1’ (open-drain
configuration), the data direction on the RB8 pin is
controlled by the TRISB9 bit instead of the TRISB8
bit.
Work around
Do not use the RB8 pin in open-drain configuration
while simultaneously using the RB9 pin.
Affected Silicon Revisions
31. Module: CPU
When a previous DISI instruction is active (i.e., the
DISICNT register is non-zero), and the value of the
DISICNT register is updated manually, the DISICNT
register freezes and disables interrupts permanently.
Work around
Avoid updating the DISICNT register manually.
Instead, use the DISI #n instruction with the
required value for ‘n’.
Affected Silicon Revisions
32. Module: CPU
When using the Signed 32-bit by 16-bit Division
instruction, div.sd, the overflow bit does not
always get set when an overflow occurs.
Work around
Test for and handle overflow conditions outside of
the div.sd instruction.
Affected Silicon Revisions
33. Module: UART
When using UTXISEL<1:0> = 01 (interrupt when last
character is shifted out of the Transmit Shift Register)
and the final character is being shifted out through
the Transmit Shift Register, the Transmit (TX)
interrupt may occur before the final bit is shifted out.
Work around
If it is critical that the interrupt processing occur
only when all transmit operations are complete,
hold off the interrupt routine processing by adding
a loop at the beginning of the routine that polls the
Transmit Shift Register Empty bit (TRMT) before
processing the rest of the interrupt.
Affected Silicon Revisions
34. Module: JTAG
JTAG Flash programming is not supported.
Work around
None.
Affected Silicon Revisions
A1 A2 A3 A4 A5
XXX
A1 A2 A3 A4 A5
XXXX
X
A1 A2 A3 A4
A5
XXXX
X
A1 A2 A3 A4 A5
XXXX
X
A1 A2 A3 A4 A5
XXXX
X
A1 A2 A3 A4
A5
XXXX
X