Information

dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04 and dsPIC33FJ128MCX02/X04
DS80372B-page 2 © 2008 Microchip Technology Inc.
11. I
2
C Module: 10-bit Addressing Mode
The 10-bit slave does not set the RBF flag or load
the I2CxRCV register, on address match if the
Least Significant bits (LSbs) of the address are the
same as the 7-bit reserved addresses.
12. UART (UxE Interrupt)
The UART error interrupt may not occur, or may
occur at an incorrect time, if multiple errors occur
during a short period of time.
13. UART Module
When the UART module is operating in 8-bit mode
(PDSEL = 0x) and using the IrDA
®
encoder/decoder
(IREN = 1), the module incorrectly transmits a data
payload of 80h as 00h.
14. Comparator Module
When CMCON<CxOUTEN> is set, the
Comparator output pin cannot be used as a
General Purpose I/O pins even if the Comparator
is disabled.
15. Internal Voltage Regulator
When the VREGS (RCON<8>) bit is set to a logic
‘0’ higher sleep current may be observed.
16. Product Identification
Revision A2 devices marked as extended
temperature range (E) devices, support only
industrial temperature range (I).
17. PSV Operations
An address error trap occurs in certain addressing
modes when accessing the first four bytes of any
PSV page.
18. ECAN Module
The ECAN module may not store received data in
the correct location.
19. ECAN Module
The ECAN module does not generate a CAN
event interrupt when coming out of Disable mode
on bus wake-up activity even if the WAKIE bit in
the CiINTE register is set.
20. Motor Control PWM – Operation in DOZE Mode
The Motor Control PWM module generates more
interrupts than expected when DOZE mode is
used and the output postscaler value is different
than 1:1.
The following sections describe the errata and work
around to these errata, where they may apply.
1. Module: Motor Control PWM – PWM
Counter Register
If the PTDIR bit is set (when PTMR is counting
down), and the CPU execution is halted (after a
breakpoint is reached), PTMR will start counting
up, as if PTDIR was zero.
Work around
None.
2. Module: UART
When the UART is configured for IR interface
operations (UxMODE<9:8> = 11), the 16x baud
clock signal on the BCLK pin is present only when
the module is transmitting. The pin is idle at all
other times.
Work around
Configure one of the output compare modules to
generate the required baud clock signal when the
UART is receiving data or in an Idle state.
3. Module: UART
When the UART is in 4x mode (BRGH = 1) and
using two Stop bits (STSEL = 1), it may sample the
first Stop bit instead of the second one.
This issue does not affect the other UART
configurations.
Work around
Use the 16x baud rate option (BRGH = 0) and
adjust the baud rate accordingly.
4. Module: SPI
The SPI transmit buffer full (SPITBF) flag does not
get set immediately after writing to the buffer.
Work around
After a write to the SPI buffer, poll the SPITBF flag
until the flag gets set, indicating that the transmit
buffer is not full. Afterwards, poll the SPITBF flag
again until the flag gets cleared, indicating that the
transmit has started and that the transmit buffer is
empty and another write can occur.