Datasheet

dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04 AND dsPIC33FJ128MCX02/X04

TABLE 4-9: 2-OUTPUT PWM2 REGISTER MAP

SFR Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State

P2TCON 05C0 PTEN

—PTSIDL— — — — — PTOPS<3:0> PTCKPS<1:0> PTMOD<1:0> 0000

P2TMR 05C2 PTDIR PWM Timer Count Value Register 0000

P2TPER 05C4

— PWM Time Base Period Register 0000

P2SECMP 05C6 SEVTDIR PWM Special Event Compare Register 0000

PWM2CON1 05C8

— — — — — — —PMOD1— — — PEN1H — — —PEN1L00FF

PWM2CON2 05CA

— — — — SEVOPS<3:0> — — — — — IUE OSYNC UDIS 0000

P2DTCON1 05CC DTBPS<1:0> DTB<5:0> DTAPS<1:0> DTA<5:0> 0000

P2DTCON2 05CE

— — — — — — — — — — — — — —DTS1ADTS1I0000

P2FLTACON 05D0

— — — — — — FAOV1H FAOV1L FLTAM — — — — — — FAEN1 0000

P2OVDCON 05D4

— — — — — — POVD1H POVD1L — — — — — — POUT1H POUT1L FF00

P2DC1 05D6 PWM Duty Cycle #1 Register 0000

Legend: — = unimplemented, read as ‘0’

TABLE 4-10: QEI1 REGISTER MAP

SFR

Name

Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State

QEI1CON 01E0 CNTERR

—

QEISIDL INDX UPDN QEIM<2:0> SWPAB PCDOUT TQGATE TQCKPS<1:0> POSRES TQCS UPDN_SRC 0000

DFLT1CON 01E2

— — — — — IMV<1:0> CEID QEOUT QECK<2:0> — — — — 0000

POS1CNT 01E4 Position Counter<15:0> 0000

MAX1CNT 01E6 Maximum Count<15:0> FFFF

Legend: — = unimplemented, read as ‘0’

TABLE 4-11: QEI2 REGISTER MAP

SFR

Name

Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State

QEI2CON 01F0 CNTERR

—

QEISIDL INDX UPDN QEIM<2:0> SWPAB PCDOUT TQGATE TQCKPS<1:0> POSRES TQCS UPDN_SRC 0000

DFLT2CON 01F2

— — — — — IMV<1:0> CEID QEOUT QECK<2:0> — — — — 0000

POS2CNT 01F4 Position Counter<15:0> 0000

MAX2CNT 01F6 Maximum Count<15:0> FFFF

Legend: — = unimplemented, read as ‘0’