Datasheet

© 2009 Microchip Technology Inc. DS70287C-page 83
dsPIC33FJXXXMCX06/X08/X10
TABLE 6-3: RESET DELAY TIMES FOR VARIOUS DEVICE RESETS
6.2.1 POR AND LONG OSCILLATOR
START-UP TIMES
The oscillator start-up circuitry and its associated delay
timers are not linked to the device Reset delays that
occur at power-up. Some crystal circuits (especially
low-frequency crystals) have a relatively long start-up
time. Therefore, one or more of the following conditions
is possible after SYSRST
is released:
• The oscillator circuit has not begun to oscillate.
• The Oscillator Start-up Timer has not expired (if a
crystal oscillator is used).
• The PLL has not achieved a lock (if PLL is used).
The device will not begin to execute code until a valid
clock source has been released to the system.
Therefore, the oscillator and PLL start-up delays must
be considered when the Reset delay time must be
known.
6.2.2 FAIL-SAFE CLOCK MONITOR
(FSCM) AND DEVICE RESETS
If the FSCM is enabled, it begins to monitor the system
clock source when SYSRST is released. If a valid clock
source is not available at this time, the device
automatically switches to the FRC oscillator and the
user can switch to the desired crystal oscillator in the
Trap Service Routine.
6.2.2.1 FSCM Delay for Crystal and PLL
Clock Sources
When the system clock source is provided by a crystal
oscillator and/or the PLL, a small delay, T
FSCM, is
automatically inserted after the POR and PWRT delay
times. The FSCM does not begin to monitor the system
clock source until this delay expires. The FSCM delay
time is nominally 500 μs and provides additional time
for the oscillator and/or PLL to stabilize. In most cases,
the FSCM delay prevents an oscillator failure trap at a
device Reset when the PWRT is disabled.
Reset Type Clock Source SYSRST
Delay
System Clock
Delay
FSCM
Delay
Notes
POR EC, FRC, LPRC TPOR + TSTARTUP + TRST ——1, 2, 3
ECPLL, FRCPLL T
POR + TSTARTUP + TRST TLOCK TFSCM 1, 2, 3, 5, 6
XT, HS, SOSC TPOR + TSTARTUP + TRST TOST TFSCM 1, 2, 3, 4, 6
XTPLL, HSPLL T
POR + TSTARTUP + TRST TOST + TLOCK TFSCM 1, 2, 3, 4, 5, 6
BOR EC, FRC, LPRC T
STARTUP + TRST ——3
ECPLL, FRCPLL T
STARTUP + TRST TLOCK TFSCM 3, 5, 6
XT, HS, SOSC TSTARTUP + TRST TOST TFSCM 3, 4, 6
XTPLL, HSPLL T
STARTUP + TRST TOST + TLOCK TFSCM 3, 4, 5, 6
MCLR
Any Clock TRST ——3
WDT Any Clock T
RST ——3
Software Any Clock TRST ——3
Illegal Opcode Any Clock T
RST ——3
Uninitialized W Any Clock T
RST ——3
Trap Conflict Any Clock TRST ——3
Note 1: T
POR = Power-on Reset delay (10 μs nominal).
2: T
STARTUP = Conditional POR delay of 20 μs nominal (if on-chip regulator is enabled) or 64 ms nominal
Power-up Timer delay (if regulator is disabled). TSTARTUP is also applied to all returns from powered-down
states, including waking from Sleep mode, if the regulator is enabled.
3: T
RST = Internal state Reset time (20 μs nominal).
4: T
OST = Oscillator Start-up Timer. A 10-bit counter counts 1024 oscillator periods before releasing the
oscillator clock to the system.
5: T
LOCK = PLL lock time (20 μs nominal).
6: TFSCM = Fail-Safe Clock Monitor delay (100 μs nominal).