Datasheet

© 2009 Microchip Technology Inc. DS70287C-page 333
dsPIC33FJXXXMCX06/X08/X10
Table Read Instructions
TBLRDH ............................................................. 70
TBLRDL .............................................................. 70
Visibility Operation ...................................................... 71
Program Memory
Interrupt Vector ........................................................... 36
Organization................................................................ 36
Reset Vector ............................................................... 36
Q
Quadrature Encoder Interface (QEI) ................................. 191
Quadrature Encoder Interface (QEI) Module
Register Map............................................................... 50
R
Reader Response ............................................................. 336
Registers
ADxCHS0 (ADCx Input Channel 0 Select................. 250
ADxCHS123 (ADCx Input Channel 1, 2, 3 Select) ... 249
ADxCON1 (ADCx Control 1)..................................... 244
ADxCON2 (ADCx Control 2)..................................... 246
ADxCON3 (ADCx Control 3)..................................... 247
ADxCON4 (ADCx Control 4)..................................... 248
ADxCSSH (ADCx Input Scan Select High)............... 251
ADxCSSL (ADCx Input Scan Select Low) ................ 251
ADxPCFGH (ADCx Port Configuration High) ........... 252
ADxPCFGL (ADCx Port Configuration Low)............. 252
CiBUFPNT1 (ECAN Filter 0-3 Buffer Pointer)........... 228
CiBUFPNT2 (ECAN Filter 4-7 Buffer Pointer)........... 229
CiBUFPNT3 (ECAN Filter 8-11 Buffer Pointer)......... 229
CiBUFPNT4 (ECAN Filter 12-15 Buffer Pointer)....... 230
CiCFG1 (ECAN Baud Rate Configuration 1) ............ 226
CiCFG2 (ECAN Baud Rate Configuration 2) ............ 227
CiCTRL1 (ECAN Control 1) ...................................... 218
CiCTRL2 (ECAN Control 2) ...................................... 219
CiEC (ECAN Transmit/Receive Error Count)............ 225
CiFCTRL (ECAN FIFO Control)................................ 221
CiFEN1 (ECAN Acceptance Filter Enable) ............... 228
CiFIFO (ECAN FIFO Status)..................................... 222
CiFMSKSEL1 (ECAN Filter 7-0 Mask Selection)..... 232,
233
CiINTE (ECAN Interrupt Enable) .............................. 224
CiINTF (ECAN Interrupt Flag)................................... 223
CiRXFnEID (ECAN Acceptance Filter n Extended Identi-
fier).................................................................... 231
CiRXFnSID (ECAN Acceptance Filter n Standard Identi-
fier).................................................................... 231
CiRXFUL1 (ECAN Receive Buffer Full 1) ................. 235
CiRXFUL2 (ECAN Receive Buffer Full 2) ................. 235
CiRXMnEID (ECAN Acceptance Filter Mask n Extended
Identifier)........................................................... 234
CiRXMnSID (ECAN Acceptance Filter Mask n Standard
Identifier)........................................................... 234
CiRXOVF1 (ECAN Receive Buffer Overflow 1) ........ 236
CiRXOVF2 (ECAN Receive Buffer Overflow 2) ........ 236
CiTRBnDLC (ECAN Buffer n Data Length Control) .. 239
CiTRBnDm (ECAN Buffer n Data Field Byte m) ....... 239
CiTRBnEID (ECAN Buffer n Extended Identifier) ..... 238
CiTRBnSID (ECAN Buffer n Standard Identifier) ...... 238
CiTRBnSTAT (ECAN Receive Buffer n Status) ........ 240
CiTRmnCON (ECAN TX/RX Buffer m Control)......... 237
CiVEC (ECAN Interrupt Code).................................. 220
CLKDIV (Clock Divisor)............................................. 148
CORCON (Core Control) ...................................... 28, 90
DFLTCON (QEI Control)........................................... 194
DMACS0 (DMA Controller Status 0)......................... 139
DMACS1 (DMA Controller Status 1) ........................ 141
DMAxCNT (DMA Channel x Transfer Count) ........... 138
DMAxCON (DMA Channel x Control)....................... 135
DMAxPAD (DMA Channel x Peripheral Address) .... 138
DMAxREQ (DMA Channel x IRQ Select) ................. 136
DMAxSTA (DMA Channel x RAM Start Address A) . 137
DMAxSTB (DMA Channel x RAM Start Address B) . 137
DSADR (Most Recent DMA RAM Address) ............. 142
DTCON1 (Dead-Time Control 1) .............................. 184
DTCON2 (Dead-Time Control 2) .............................. 185
FLTACON (Fault A Control) ..................................... 186
FLTBCON (Fault B Control) ..................................... 187
I2CxCON (I2Cx Control)........................................... 203
I2CxMSK (I2Cx Slave Mode Address Mask)............ 207
I2CxSTAT (I2Cx Status) ........................................... 205
ICxCON (Input Capture x Control)............................ 172
IEC0 (Interrupt Enable Control 0) ............................. 103
IEC1 (Interrupt Enable Control 1) ............................. 105
IEC2 (Interrupt Enable Control 2) ............................. 107
IEC3 (Interrupt Enable Control 3) ............................. 109
IEC4 (Interrupt Enable Control 4) ............................. 111
IFS0 (Interrupt Flag Status 0) ..................................... 94
IFS1 (Interrupt Flag Status 1) ..................................... 96
IFS2 (Interrupt Flag Status 2) ..................................... 98
IFS3 (Interrupt Flag Status 3) ................................... 100
IFS4 (Interrupt Flag Status 4) ................................... 102
INTCON1 (Interrupt Control 1) ................................... 91
INTCON2 (Interrupt Control 2) ................................... 93
INTTREG Interrupt Control and Status Register ...... 130
IPC0 (Interrupt Priority Control 0) ............................. 112
IPC1 (Interrupt Priority Control 1) ............................. 113
IPC10 (Interrupt Priority Control 10) ......................... 122
IPC11 (Interrupt Priority Control 11) ......................... 123
IPC12 (Interrupt Priority Control 12) ......................... 124
IPC13 (Interrupt Priority Control 13) ......................... 125
IPC14 (Interrupt Priority Control 14) ......................... 126
IPC15 (Interrupt Priority Control 15) ......................... 127
IPC16 (Interrupt Priority Control 16) ......................... 128
IPC17 (Interrupt Priority Control 17) ......................... 129
IPC2 (Interrupt Priority Control 2) ............................. 114
IPC3 (Interrupt Priority Control 3) ............................. 115
IPC4 (Interrupt Priority Control 4) ............................. 116
IPC5 (Interrupt Priority Control 5) ............................. 117
IPC6 (Interrupt Priority Control 6) ............................. 118
IPC7 (Interrupt Priority Control 7) ............................. 119
IPC8 (Interrupt Priority Control 8) ............................. 120
IPC9 (Interrupt Priority Control 9) ............................. 121
NVMCOM (Flash Memory Control) ............................ 75
OCxCON (Output Compare x Control) ..................... 175
OSCCON (Oscillator Control)................................... 146
OSCTUN (FRC Oscillator Tuning)............................ 150
OVDCON (Override Control) .................................... 188
PDC1 (PWM Duty Cycle 1) ...................................... 189
PDC2 (PWM Duty Cycle 2) ...................................... 189
PDC3 (PWM Duty Cycle 3) ...................................... 190
PDC4 (PWM Duty Cycle 4) ...................................... 190
PLLFBD (PLL Feedback Divisor) ............................. 149
PMD1 (Peripheral Module Disable Control Register 1) ..
155
PMD2 (Peripheral Module Disable Control Register 2) ..
157
PMD3 (Peripheral Module Disable Control Register 3) ..
159
PTCON (PWM Time Base Control) .......................... 179
PTMR (PWM Timer Count Value) ............................ 180