Datasheet
dsPIC33FJXXXMCX06/X08/X10
DS70287C-page 326 © 2009 Microchip Technology Inc.
Section 8.0 “Oscillator Configuration” Updated the third clock source item (External Clock) in
Section 8.1.1 “System Clock Sources”.
Added the center frequency in the OSCTUN register for the FRC
Tuning bits (TUN<5:0>) value 011111 and updated the center
frequency for bits value 011110 (Register 8-4).
Section 15.0 “Motor Control PWM Module” Removed sections 15.1 through 15.16 (redundant information,
which is now available in the related section in the “dsPIC33F
Family Reference Manual”).
Updated SFR names in the PWM Module Block Diagram (Figure 15-
1).
Updated all register names (Register 16-1 through Register 15-15).
Section 16.0 “Quadrature Encoder
Interface (QEI) Module”
Removed sections 16.1 through 16.9 (redundant information, which
is now available in the related section in the “dsPIC33F Family
Reference Manual”).
Updated names in Quadrature Encoder Interface Block Diagram
(Figure 16-1).
Updated register names (Register 16-1 and Register 16-2).
Section 17.0 “Serial Peripheral Interface
(SPI)”
Removed redundant information, which is now available in the
related section in the “dsPIC33F Family Reference Manual”.
Section 18.0 “Inter-Integrated Circuit™
(I
2
C™)”
Removed sections 18.3 through 18.14, while retaining the I
2
C Block
Diagram (Figure 18-1) (redundant information, which is now
available in the related section in the “dsPIC33F Family Reference
Manual”).
Section 19.0 “Universal Asynchronous
Receiver Transmitter (UART)”
Removed sections 19.1 through 19.7 (redundant information, which
is now available in the related section in the “dsPIC33F Family
Reference Manual”).
Section 20.0 “Enhanced CAN (ECAN™)
Module”
Removed sections 20.4 through 20.6 (redundant information, which
is now available in the related section in the “dsPIC33F Family
Reference Manual”).
Updated Baud Rate Prescaler (BRP<5:0>) bit values in the CiCFG1
register (Register 20-9).
Changed default bit value from ‘0’ to ‘1’ for bits 6 through 15
(FLTEN6-FLTEN15) in the CiFEN1 register (Register 20-11).
Section 21.0 “10-Bit/12-Bit Analog-to-
Digital Converter (ADC)”
Removed Equation 21-1 (ADC Conversion Clock Period) and Figure
21-3 (ADC Transfer Function (10-Bit Example) in Section 21.0 “10-
bit/12-bit Analog-to-Digital Converter (ADC)”
Updated AN14 and AN15 ADC values in the ADC2 Module Block
Diagram (Figure 21-2).
Added Note 2 to ADC Conversion Clock Period Block Diagram
(Figure 21-3).
Added Note to ADxCHS0 register (Register 21-6).
Updated ADC Conversion Clock Select bits in the ADxCON3
register from ADCS<5:0> to ADCS<7:0>. Any references to these
bits have also been updated throughout this data sheet
(Register 21-3).
TABLE A-1: MAJOR SECTION UPDATES (CONTINUED)
Section Name Update Description