Datasheet

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
DS70292G-page 422 © 2007-2012 Microchip Technology Inc.
Revision E (January 2011)
This includes typographical and formatting changes
throughout the data sheet text. In addition, the
Preliminary marking in the footer was removed.
All instances of V
DDCORE have been removed.
All other major changes are referenced by their
respective section in the following table.
TABLE A-4: MAJOR SECTION UPDATES
Section Name Update Description
“High-Performance, 16-bit Digital Signal
Controllers”
The high temperature end range was updated to +150ºC (see
“Operating Range:”).
Section 2.0 “Guidelines for Getting Started
with 16-bit Digital Signal Controllers”
Updated the title of Section 2.3 “CPU Logic Filter Capacitor
Connection (VCAP)”.
The frequency limitation for device PLL start-up conditions was
updated in Section 2.7 “Oscillator Value Conditions on Device
Start-up”.
The second paragraph in Section 2.9 “Unused I/Os” was updated.
Section 4.0 “Memory Organization” The All Resets values for the following SFRs in the Timer Register
Map were changed (see Table 4-5):
•TMR1
•TMR2
•TMR3
•TMR4
•TMR5
Section 9.0 “Oscillator Configuration” Added Note 3 to the OSCCON: Oscillator Control Register (see
Register 9-1).
Added Note 2 to the CLKDIV: Clock Divisor Register (see
Register 9-2).
Added Note 1 to the PLLFBD: PLL Feedback Divisor Register (see
Register 9-3).
Added Note 2 to the OSCTUN: FRC Oscillator Tuning Register (see
Register 9-4).
Added Note 1 to the ACLKCON: Auxiliary Control Register (see
Register 9-5).
Section 21.0 “10-bit/12-bit Analog-to-Digital
Converter (ADC)”
Updated the V
REFL references in the ADC1 module block diagrams
(see Figure 21-1 and Figure 21-2).
Section 27.0 “Special Features” Added a new paragraph and removed the third paragraph in
Section 27.1 “Configuration Bits”.
Added the column “RTSP Effects” to the dsPIC33F Configuration
Bits Descriptions (see Table 27-2).