Datasheet

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
DS70292G-page 264 © 2007-2012 Microchip Technology Inc.
FIGURE 21-1: ADC1 MODULE BLOCK DIAGRAM FOR dsPIC33FJ32GP304,
dsPIC33FJ64GP204/804 AND dsPIC33FJ128GP204/804 DEVICES
S/H0
S/H1
ADC1BUF0
AN0
AN12
AN1
VREFL
CH0SB<4:0>
CH0NA
CH0NB
+
-
AN0
AN3
CH123SA
AN9
VREFL
CH123SB
CH123NA
CH123NB
AN6
+
-
S/H2
AN1
AN4
CH123SA
AN10
VREFL
CH123SB
CH123NA
CH123NB
AN7
+
-
S/H3
AN2
AN5
CH123SA
AN11
VREFL
CH123SB
CH123NA
CH123NB
AN8
+
-
CH1
(2)
CH0
CH2
(2)
CH3
(2)
CH0SA<4:0>
CHANNEL
SCAN
CSCNA
Alternate
Note 1: VREF+, VREF- inputs can be multiplexed with other analog inputs.
2: Channels 1, 2 and 3 are not applicable for the 12-bit mode of operation.
Input Selection
VCFG<2:0>
AVDD
AVSS
VREF-
(1)
VREF+
(1)
SAR ADC
V
REFH
VREFL