Datasheet

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
DS70292G-page 238 © 2007-2012 Microchip Technology Inc.
REGISTER 19-7: CiINTE: ECAN™ INTERRUPT ENABLE REGISTER
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
IVRIE WAKIE ERRIE
— FIFOIE RBOVIE RBIE TBIE
bit 7 bit 0
Legend: C = Writable bit, but only ‘0’ can be written to clear the bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-8 Unimplemented: Read as ‘0’
bit 7 IVRIE: Invalid Message Received Interrupt Enable bit
1 = Interrupt Request Enabled
0 = Interrupt Request not enabled
bit 6 WAKIE: Bus Wake-up Activity Interrupt Flag bit
1 = Interrupt Request Enabled
0 = Interrupt Request not enabled
bit 5 ERRIE: Error Interrupt Enable bit
1 = Interrupt Request Enabled
0 = Interrupt Request not enabled
bit 4 Unimplemented: Read as ‘0’
bit 3 FIFOIE: FIFO Almost Full Interrupt Enable bit
1 = Interrupt Request Enabled
0 = Interrupt Request not enabled
bit 2 RBOVIE: RX Buffer Overflow Interrupt Enable bit
1 = Interrupt Request Enabled
0 = Interrupt Request not enabled
bit 1 RBIE: RX Buffer Interrupt Enable bit
1 = Interrupt Request Enabled
0 = Interrupt Request not enabled
bit 0 TBIE: TX Buffer Interrupt Enable bit
1 = Interrupt Request Enabled
0 = Interrupt Request not enabled