Datasheet

© 2007-2012 Microchip Technology Inc. DS70292G-page 233
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 19-2: CiCTRL2: ECAN™ CONTROL REGISTER 2
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 U-0 R-0 R-0 R-0 R-0 R-0
— — — DNCNT<4:0>
bit 7 bit 0
Legend: C = Writable bit, but only ‘0’ can be written to clear the bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-5 Unimplemented: Read as ‘0’
bit 4-0 DNCNT<4:0>: DeviceNet™ Filter Bit Number bits
10010-11111 = Invalid selection
10001 = Compare up to data byte 3, bit 6 with EID<17>
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•
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00001 = Compare up to data byte 1, bit 7 with EID<0>
00000 = Do not compare data bytes