Datasheet

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
DS70292G-page 136 © 2007-2012 Microchip Technology Inc.
REGISTER 8-7: DMACS0: DMA CONTROLLER STATUS REGISTER 0
R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0
PWCOL7 PWCOL6 PWCOL5 PWCOL4 PWCOL3 PWCOL2 PWCOL1 PWCOL0
bit 15 bit 8
R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0
XWCOL7 XWCOL6 XWCOL5 XWCOL4 XWCOL3 XWCOL2 XWCOL1 XWCOL0
bit 7 bit 0
Legend: C = Clear only bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 PWCOL7: Channel 7 Peripheral Write Collision Flag bit
1 = Write collision detected
0 = No write collision detected
bit 14 PWCOL6: Channel 6 Peripheral Write Collision Flag bit
1 = Write collision detected
0 = No write collision detected
bit 13 PWCOL5: Channel 5 Peripheral Write Collision Flag bit
1 = Write collision detected
0 = No write collision detected
bit 12 PWCOL4: Channel 4 Peripheral Write Collision Flag bit
1 = Write collision detected
0 = No write collision detected
bit 11 PWCOL3: Channel 3 Peripheral Write Collision Flag bit
1 = Write collision detected
0 = No write collision detected
bit 10 PWCOL2: Channel 2 Peripheral Write Collision Flag bit
1 = Write collision detected
0 = No write collision detected
bit 9 PWCOL1: Channel 1 Peripheral Write Collision Flag bit
1 = Write collision detected
0 = No write collision detected
bit 8 PWCOL0: Channel 0 Peripheral Write Collision Flag bit
1 = Write collision detected
0 = No write collision detected
bit 7 XWCOL7: Channel 7 DMA RAM Write Collision Flag bit
1 = Write collision detected
0 = No write collision detected
bit 6 XWCOL6: Channel 6 DMA RAM Write Collision Flag bit
1 = Write collision detected
0 = No write collision detected
bit 5 XWCOL5: Channel 5 DMA RAM Write Collision Flag bit
1 = Write collision detected
0 = No write collision detected
bit 4 XWCOL4: Channel 4 DMA RAM Write Collision Flag bit
1 = Write collision detected
0 = No write collision detected