Datasheet

© 2007-2012 Microchip Technology Inc. DS70292G-page 133
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 8-2: DMAxREQ: DMA CHANNEL x IRQ SELECT REGISTER
R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
FORCE
(1)
— — — — — — —
bit 15 bit 8
U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— IRQSEL6<6:0>
(2)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 FORCE: Force DMA Transfer bit
(1)
1 = Force a single DMA transfer (Manual mode)
0 = Automatic DMA transfer initiation by DMA request
bit 14-7 Unimplemented: Read as ‘0’
bit 6-0 IRQSEL<6:0>: DMA Peripheral IRQ Number Select bits
(2)
1111111 = DMAIRQ127 selected to be Channel DMAREQ
.
.
.
0000000 = DMAIRQ0 selected to be Channel DMAREQ
Note 1: The FORCE bit cannot be cleared by the user. The FORCE bit is cleared by hardware when the forced
DMA transfer is complete.
2: Refer to Ta bl e 7-1 for a complete listing of IRQ numbers for all interrupt sources.