Datasheet

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
DS70292G-page 100 © 2007-2012 Microchip Technology Inc.
REGISTER 7-7: IFS2: INTERRUPT FLAG STATUS REGISTER 2
U-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0
—DMA4IFPMPIF— — — — —
bit 15 bit 8
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — —DMA3IFC1IF
(1)
C1RXIF
(1)
SPI2IF SPI2EIF
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 Unimplemented: Read as ‘0’
bit 14 DMA4IF: DMA Channel 4 Data Transfer Complete Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 13 PMPIF: Parallel Master Port Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 12-5 Unimplemented: Read as ‘0’
bit 4 DMA3IF: DMA Channel 3 Data Transfer Complete Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 3 C1IF: ECAN1 Event Interrupt Flag Status bit
(1)
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 2 C1RXIF: ECAN1 Receive Data Ready Interrupt Flag Status bit
(1)
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 1 SPI2IF: SPI2 Event Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 0 SPI2EIF: SPI2 Error Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
Note 1: Interrupts are disabled on devices without ECAN™ modules.