Datasheet

ManualsBrandsMICROCHIP TECHNOLOGY ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller QFN 28 S (6x6) 16-Bit 40 null I/O number 21

421

422

423

424

425

426

427

428

429

430

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04

Listen All Messages .................................................. 230

Listen Only ................................................................ 230

Loopback .................................................................. 230

Normal Operation...................................................... 230

Modulo Addressing ............................................................. 63

Applicability ................................................................. 64

Operation Example ..................................................... 63

Start and End Address................................................ 63

W Address Register Selection .................................... 63

MPLAB ASM30 Assembler, Linker, Librarian ................... 334

MPLAB Integrated Development Environment Software .. 333

MPLAB PM3 Device Programmer .................................... 336

MPLAB REAL ICE In-Circuit Emulator System................. 335

MPLINK Object Linker/MPLIB Object Librarian ................ 334

NVM Module

Open-Drain Configuration ................................................. 160

Output Compare ............................................................... 203

Packaging ......................................................................... 407

Marking ..................................................................... 407

Peripheral Module Disable (PMD) .................................... 154

Pinout I/O Descriptions (table) ............................................ 15

PMD Module

PORTA

PORTB

Power-on Reset (POR) ....................................................... 83

Power-Saving Features .................................................... 153

Clock Frequency and Switching................................ 153

Program Address Space..................................................... 35

Construction................................................................ 66

Data Access from Program Memory Using

Program Space Visibility..................................... 69

Data Access from Program Memory Using

Table Instructions ............................................... 68

Data Access from, Address Generation...................... 67

Memory Map ............................................................... 35

Table Read Instructions

TBLRDH ............................................................. 68

TBLRDL .............................................................. 68

Visibility Operation ...................................................... 69

Program Memory

Interrupt Vector ........................................................... 36

Organization................................................................ 36

Reset Vector ............................................................... 36

Reader Response ............................................................. 432

CRC ............................................................................ 58

Dual Comparator......................................................... 58

Parallel Master/Slave Port .......................................... 57

Real-Time Clock and Calendar................................... 58

Registers

AD1CHS0 (ADC1 Input Channel 0 Select ................ 274

AD1CHS123 (ADC1 Input Channel 1, 2, 3 Select) ... 273

AD1CON1 (ADC1 Control 1) .................................... 268

AD1CON2 (ADC1 Control 2) .................................... 270

AD1CON3 (ADC1 Control 3) .................................... 271

AD1CON4 (ADC1 Control 4) .................................... 272

AD1CSSL (ADC1 Input Scan Select Low) ............... 275

AD1PCFGL (ADC1 Port Configuration Low) ............ 275

CiBUFPNT1 (ECAN Filter 0-3 Buffer Pointer) .......... 241

CiBUFPNT2 (ECAN Filter 4-7 Buffer Pointer) .......... 242

CiBUFPNT3 (ECAN Filter 8-11 Buffer Pointer) ........ 242

CiBUFPNT4 (ECAN Filter 12-15 Buffer Pointer) ...... 243

CiCFG1 (ECAN Baud Rate Configuration 1)............ 239

CiCFG2 (ECAN Baud Rate Configuration 2)............ 240

CiCTRL1 (ECAN Control 1)...................................... 232

CiCTRL2 (ECAN Control 2)...................................... 233

CiEC (ECAN Transmit/Receive Error Count) ........... 239

CiFCTRL (ECAN FIFO Control) ............................... 235

CiFEN1 (ECAN Acceptance Filter Enable)............... 241

CiFIFO (ECAN FIFO Status) .................................... 236

CiFMSKSEL1 (ECAN Filter 7-0 Mask Selection) .... 245,

246

CiINTE (ECAN Interrupt Enable) .............................. 238

CiINTF (ECAN Interrupt Flag) .................................. 237

CiRXFnEID (ECAN Acceptance Filter n

Extended Identifier) .......................................... 245

CiRXFnSID (ECAN Acceptance Filter n

Standard Identifier) ........................................... 244

CiRXFUL1 (ECAN Receive Buffer Full 1)................. 248

CiRXFUL2 (ECAN Receive Buffer Full 2)................. 248

CiRXMnEID (ECAN Acceptance Filter Mask n

Extended Identifier) .......................................... 247

CiRXMnSID (ECAN Acceptance Filter Mask n

Standard Identifier) ........................................... 247

CiRXOVF1 (ECAN Receive Buffer Overflow 1)........ 249

CiRXOVF2 (ECAN Receive Buffer Overflow 2)........ 249

CiTRBnSID (ECAN Buffer n Standard Identifier)..... 251,

252, 254

CiTRmnCON (ECAN TX/RX Buffer m Control) ........ 250

CiVEC (ECAN Interrupt Code) ................................. 234

CLKDIV (Clock Divisor) ............................................ 147

CORCON (Core Control)...................................... 29, 92

DCICON1 (DCI Control 1) ........................................ 257

DCICON2 (DCI Control 2) ........................................ 258

DCICON3 (DCI Control 3) ........................................ 259

DCISTAT (DCI Status) ............................................. 260

DMACS0 (DMA Controller Status 0) ........................ 136

DMACS1 (DMA Controller Status 1) ........................ 138

DMAxCNT (DMA Channel x Transfer Count) ........... 135

DMAxCON (DMA Channel x Control)....................... 132

DMAxPAD (DMA Channel x Peripheral Address) .... 135

DMAxREQ (DMA Channel x IRQ Select) ................. 133

DMAxSTA (DMA Channel x RAM Start Address A) . 134

DMAxSTB (DMA Channel x RAM Start Address B) . 134

DSADR (Most Recent DMA RAM Address) ............. 139

I2CxCON (I2Cx Control)........................................... 216

I2CxMSK (I2Cx Slave Mode Address Mask)............ 220

I2CxSTAT (I2Cx Status) ........................................... 218

IFS0 (Interrupt Flag Status 0) ............................. 96, 103

IFS1 (Interrupt Flag Status 1) ............................. 98, 105

IFS2 (Interrupt Flag Status 2) ........................... 100, 107

IFS3 (Interrupt Flag Status 3) ........................... 101, 108

IFS4 (Interrupt Flag Status 4) ........................... 102, 109

INTCON1 (Interrupt Control 1) ................................... 93

INTCON2 (Interrupt Control 2) ................................... 95

INTTREG Interrupt Control and Status Register ...... 126

IPC0 (Interrupt Priority Control 0) ............................. 110

IPC1 (Interrupt Priority Control 1) ............................. 111

IPC11 (Interrupt Priority Control 11) ......................... 120

IPC14 (Interrupt Priority Control 14) ......................... 121

IPC15 (Interrupt Priority Control 15) ......................... 122

IPC16 (Interrupt Priority Control 16) ......................... 123