Datasheet

© 2007-2012 Microchip Technology Inc. DS70292G-page 247
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 19-20: CiRXMnSID: ECAN™ ACCEPTANCE FILTER MASK STANDARD IDENTIFIER
REGISTER n (n = 0-2)
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3
bit 15 bit 8
R/W-x R/W-x R/W-x U-0 R/W-x U-0 R/W-x R/W-x
SID2 SID1 SID0
—MIDE —EID17EID16
bit 7 bit 0
Legend: C = Writable bit, but only ‘0’ can be written to clear the bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-5 SID<10:0>: Standard Identifier bits
1 = Include bit SIDx in filter comparison
0 = Bit SIDx is don’t care in filter comparison
bit 4 Unimplemented: Read as ‘0’
bit 3 MIDE: Identifier Receive Mode bit
1 = Match only message types (standard or extended address) that correspond to EXIDE bit in filter
0 = Match either standard or extended address message if filters match
(i.e., if (Filter SID) = (Message SID) or if (Filter SID/EID) = (Message SID/EID))
bit 2 Unimplemented: Read as ‘0’
bit 1-0 EID<17:16>: Extended Identifier bits
1 = Include bit EIDx in filter comparison
0 = Bit EIDx is don’t care in filter comparison
REGISTER 19-21: CiRXMnEID: ECAN™ ACCEPTANCE FILTER MASK EXTENDED IDENTIFIER
REGISTER n (n = 0-2)
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8
bit 15 bit 8
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0
bit 7 bit 0
Legend: C = Writable bit, but only ‘0’ can be written to clear the bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 EID<15:0>: Extended Identifier bits
1 = Include bit EIDx in filter comparison
0 = Bit EIDx is don’t care in filter comparison