Datasheet

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
DS70292G-page 122 © 2007-2012 Microchip Technology Inc.
REGISTER 7-27: IPC15: INTERRUPT PRIORITY CONTROL REGISTER 15
U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0
— — — — — RTCIP<2:0>
bit 15 bit 8
U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0
— DMA5IP<2:0> —DCIIP<2:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-11 Unimplemented: Read as ‘0’
bit 10-8 RTCIP<2:0>: Real-Time Clock and Calendar Interrupt Flag Status bits
111 = Interrupt is priority 7 (highest priority interrupt)
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001 = Interrupt is priority 1
000 = Interrupt source is disabled
bit 7 Unimplemented: Read as ‘0’
bit 6-4 DMA5IP<2:0>: DMA Channel 5 Data Transfer Complete Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)
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•
•
001 = Interrupt is priority 1
000 = Interrupt source is disabled
bit 3-0 DCIIP<2:0>: DCI Event Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)
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•
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001 = Interrupt is priority 1
000 = Interrupt source is disabled