Information

 2009-2013 Microchip Technology Inc. DS80000443K-page 7
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04 and dsPIC33FJ128GPX02/X04
12. Module: UART
When the UARTx is operating in 8-bit mode
(PDSEL<1:0> = 0x) and using the IrDA encoder/
decoder (IREN = 1), the module incorrectly
transmits a data payload of 80h as 00h.
Work around
None.
Affected Silicon Revisions
13. Module: Comparator
If the CxOUTEN (CMCON) bit is set and the
comparator module, CxEN (CMCON) bit, is
disabled, the remappable comparator output pins,
C1OUT and C2OUT, cannot be used as general
purpose I/O pins.
Work around
When the comparator module is disabled, the
CxOUTEN bit should be reset so that the
remappable comparator output pins, C1OUT and
C2OUT, are not driven onto the output pad.
Affected Silicon Revisions
14. Module: Internal Voltage Regulator
When the VREGS bit (RCON<8>) is set to a logic
‘0’, the device may reset and a higher Sleep
current may be observed.
Work around
Ensure that the VREGS bit (RCON<8>) is set to a
logic ‘1’ for device Sleep mode operation.
Affected Silicon Revisions
15. Module: PSV Operations
An address error trap occurs in certain addressing
modes when accessing the first four bytes of a
PSV page. This only occurs when using the
following addressing modes:
• MOV.D
• Register Indirect Addressing (Word or Byte
mode) with pre/post-decrement
Work around
Do not perform PSV accesses to any of the first
four bytes using the above addressing modes. For
applications using the C language, MPLAB
®
C30
Version 3.11 or higher, provides the following
command-line switch that implements a work
around for the erratum.
-merrata=psv_trap
Refer to the readme.txt file in the MPLAB C30
v3.11 toolsuite for further details.
Affected Silicon Revisions
16. Module: ECAN™
The WAKIF bit in the CiINTF register cannot be
cleared by software instructions after the device is
interrupted from Sleep due to activity on the CAN
bus.
When the device wakes up from Sleep due to CAN
bus activity, the ECAN module is placed in
operational mode. The ECAN event interrupt
occurs due to the WAKIF flag. Trying to clear the
flag in the Interrupt Service Routine (ISR) may not
clear the flag. The WAKIF bit being set will not
cause repetitive Interrupt Service Routine
execution.
Work around
Although the WAKIF bit does not clear, the device
Sleep and ECAN wake function continue to work
as expected. If the ECAN event is enabled, the
CPU will enter the Interrupt Service Routine due to
the WAKIF flag getting set. The application can
maintain a secondary flag, which tracks the device
Sleep and wake events.
Affected Silicon Revisions
A1 A2 A3 A4 A5
XXXX
X
A1 A2 A3 A4
A5
XXXX
X
A1 A2 A3 A4
A5
XXXX
X
A1 A2 A3 A4 A5
XXXX
X
A1 A2 A3 A4
A5
XXXX
X