Information

 2009-2013 Microchip Technology Inc. DS80000443K-page 5
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04 and dsPIC33FJ128GPX02/X04
Silicon Errata Issues
1. Module: UART
When the UARTx is configured for IR interface
operations (UxMODE<9:8> = 11), the 16x baud
clock signal on the BCLK pin is present only when
the module is transmitting. The pin is Idle at all
other times.
Work around
Configure one of the output compare modules to
generate the required baud clock signal when the
UARTx is receiving data or in an Idle state.
Affected Silicon Revisions
2. Module: UART
When the UART is in 4x mode (BRGH = 1) and
using two Stop bits (STSEL = 1), it may sample the
first Stop bit instead of the second one.
This issue does not affect the other UARTx
configurations.
Work around
Use the 16x baud rate option (BRGH = 0) and
adjust the baud rate accordingly.
Affected Silicon Revisions
3. Module: SPI
The SPIx Transmit Buffer Full (SPITBF) flag does
not get set immediately after writing to the buffer.
Work around
After a write to the SPIx buffer, poll the SPITBF flag
until the flag gets set, indicating that the transmit
buffer is not full. Afterwards, poll the SPITBF flag
again until the flag gets cleared, indicating that the
transmit has started and that the transmit buffer is
empty, and another write can occur.
Affected Silicon Revisions
4. Module: SPI
The SPIx module will generate incorrect frame
synchronization pulses when configured in Frame
Master mode if the start of data is selected to
coincide with the start of the frame synchronization
pulse (FRMEN = 1, SPIFSD = 0, FRMDLY = 1).
However, the module functions correctly in Frame
Slave mode and also in Frame Master mode if
FRMDLY = 0.
Work around
If DMA is not being used, manually drive the SSx
pin (x = 1 or 2) high, using the associated PORT
register, and then drive it low after the required
1 bit time pulse width. This operation needs to be
performed when the transmit buffer is written.
If DMA is being used, and if no other peripheral
modules are using DMA transfers, use a timer
interrupt to periodically generate the frame
synchronization pulse (using the method
described above) after every 8 or 16-bit period
(depending on the data word size configured using
the MODE16 bit).
If FRMDLY = 0, no work around is needed.
Affected Silicon Revisions
5. Module: I
2
C™
The BCL bit in I2CxSTAT can only be cleared with
word instructions, and can be corrupted with byte
instructions and bit operations.
Work around
Use word instructions to clear BCL.
Affected Silicon Revisions
Note: This document summarizes all silicon
errata issues from all revisions of silicon,
previous as well as current. Only the
issues indicated by the shaded column in
the following tables apply to the current
silicon revision (A5).
A1 A2 A3 A4
A5
XXXX
X
A1 A2 A3 A4
A5
XXXX
X
A1 A2 A3 A4 A5
XXXX
X
A1 A2 A3 A4 A5
XXXX
X
A1 A2 A3 A4
A5
XXXX
X