Information

ManualsBrandsMICROCHIP TECHNOLOGY ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller SOIC 28 16-Bit 40 null I/O number 21

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04 and dsPIC33FJ128GPX02/X04

DS80000443K-page 4  2009-2013 Microchip Technology Inc.

ECAN™ Sleep Mode 16. The WAKIF bit in the CiINTF register cannot be

cleared by software instruction after the device is

interrupted from Sleep due to activity on the CAN bus.

XXXXX

ECAN Receive

Operation

17. The ECAN module may not store the received data in

the correct location.

XXX

CPU EXCH

Instruction

18. The EXCH instruction does not execute correctly. XXXXX

SPI Transmit

Operation

19. Writing to the SPIxBUF register as soon as the TBF bit

is cleared will cause the SPIx module to ignore the

written data.

XXXXX

UART Break

Character

Generation

20. The UARTx module will not generate back-to-back

Break characters.

XXXXX

Audio DAC Voltage

Specifications

21. The audio DAC positive and negative output

differential voltages may not meet the specifications

listed in the data sheet.

XXX

ADC Current

Consumption

in Sleep Mode

22. If the ADC module is in an enabled state when the

device enters Sleep mode, the Power-Down (I

PD)

current of the device may exceed the device data

sheet specifications.

XXXXX

JTAG Boundary

Scan

23. On 28-pin devices, boundary scan does not function

correctly for Pin 7.

XXXXX

RTCC Operation

During Reset

24. The RTCC module gets reset on any device Reset,

instead of getting reset only on a POR or BOR.

XXXXX

Core 150ºC

Operation

25. These revisions of silicon only support 140°C

operation instead of 150°C for High-Temp operating

temperature.

XXX

I/O Port Data Direction

Setting

26. When the RB8 pin is in open-drain configuration, the

data direction depends upon the TRISB9 bit instead of

the TRISB8 bit.

XXXXX

CPU Interrupt

Disable

27. When a previous DISI instruction is active (i.e., the

DISICNT register is non-zero), and the value of the

DISICNT register is updated manually, the DISICNT

XXXXX

CPU div.sd 28. When using the div.sd instruction, the overflow bit is

not getting set when an overflow occurs.

XXXXX

UART TX Interrupt 29. A Transmit (TX) interrupt may occur before the data

transmission is complete.

XXXXX

JTAG Flash

Programming

30. JTAG Flash programming is not supported. XXXXX

TABLE 2: SILICON ISSUE SUMMARY (CONTINUED)

Module Feature

Item

Number

Issue Summary

Affected

Revisions

(1)

A1 A2 A3 A4 A5

Note 1: Only those issues indicated in the last column apply to the current silicon revision.