Information

ManualsBrandsMICROCHIP TECHNOLOGY ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller SOIC 28 16-Bit 40 null I/O number 21

dsPIC33FJ32GP302/304,

dsPIC33FJ64GPX02/X04 and

dsPIC33FJ128GPX02/X04

The dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/

X04 and dsPIC33FJ128GPX02/X04 (Rev. A1/A2/A3)

devices you have received were found to conform to

the specifications and functionality described in the

following documents:

• DS70292 – “dsPIC33FJ32GP302/304,

dsPIC33FJ64GPX02/X04 and

dsPIC33FJ128GPX02/X04 Data Sheet”

• DS70157 – “dsPIC30F/33F Programmer’s

Reference Manual”

The exceptions to the specifications in the documents

listed above are described in this section. The specific

devices for which these exceptions are described are

listed below:

• dsPIC33FJ128GP804

• dsPIC33FJ128GP802

• dsPIC33FJ128GP204

• dsPIC33FJ128GP202

• dsPIC33FJ64GP804

• dsPIC33FJ64GP802

• dsPIC33FJ64GP204

• dsPIC33FJ64GP202

• dsPIC33FJ32GP304

• dsPIC33FJ32GP302

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04

and dsPIC33FJ128GPX02/X04 Rev. A1/A2/A3 silicon

is identified by performing a “Reset and Connect”

operation to the device using MPLAB

ICD 2 with

MPLAB IDE v7.40 or later. The output window will show

a successful connection to the device specified in

Configure>Select Device

. The resulting DEVREV

0x3002 and 0x3003, respectively.

The errata described in this document will be

addressed in future revisions of silicon.

Silicon Errata Summary

The following list summarizes the errata described in

further detail in the remainder of this document:

1. UART Module

The 16x baud clock signal on the BCLK pin is

present only when the module is transmitting.

2. UART Module

When the UART is in 4x mode (BRGH = 1) and

using two Stop bits (STSEL = 1), it may sample the

first Stop bit instead of the second one.

3. SPI Module

The SPI transmit buffer full (SPITBF) flag does not

get set immediately after writing to the buffer.

4. SPI Module in Frame Master Mode

The SPI module will generate incorrect frame

synchronization pulses in Frame Master mode if

FRMDLY = 1.

5. I

C™ Module

The BCL bit in I2CSTAT can only be cleared with

Word instructions, and can be corrupted with byte

instructions and bit operations.

6. I

C Module

The ACKSTAT bit is cleared shortly after being set

following a slave transmit.

7. I

C Module: 10-bit Addressing Mode

When the I

C module is configured for 10-bit

addressing using the same address bits (A10 and

A9) as other I

C devices, the A10 and A9 bits may

not work as expected.

8. I

C Module: 10-bit Addressing Mode

When the I

C module is configured as a 10-bit

slave with an address of 0x102, the I2CxRCV

rather than 0x02.

9. I

C Module

With the I

C module enabled, the PORT bits and

external Interrupt Input functions (if any)

associated with SCL and SDA pins will not reflect

the actual digital logic levels on the pins.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04 and

dsPIC33FJ128GPX02/X04 Rev. A1/A2/A3 Silicon Errata

Summary of content (8 pages)

PAGE 1
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04 and dsPIC33FJ128GPX02/X04 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04 and dsPIC33FJ128GPX02/X04 Rev. A1/A2/A3 Silicon Errata The dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/ X04 and dsPIC33FJ128GPX02/X04 (Rev.
PAGE 2
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04 and dsPIC33FJ128GPX02/X04 10. I2C Module: 10-bit Addressing Mode The 10-bit slave does not set the RBF flag or load the I2CxRCV register, on address match if the Least Significant bits (LSbs) of the address are the same as the 7-bit reserved addresses. 11. UART (UxE Interrupt) The UART error interrupt may not occur, or may occur at an incorrect time, if multiple errors occur during a short period of time. 12.
PAGE 3
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04 and dsPIC33FJ128GPX02/X04 4. Module: SPI The SPI module will generate incorrect frame synchronization pulses when configured in Frame Master mode if the start of data is selected to coincide with the start of the frame synchronization pulse (FRMEN = 1, SPIFSD = 0, FRMDLY = 1). However, the module functions correctly in Frame Slave mode, and also in Frame Master mode if FRMDLY = 0.
PAGE 4
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04 and dsPIC33FJ128GPX02/X04 11. Module: UART (UxE Interrupt) The UART error interrupt may not occur, or may occur at an incorrect time, if multiple errors occur during a short period of time. Work around Read the error flags in the UxSTA register whenever a byte is received to verify the error status. In most cases, these bits will be correct, even if the UART error interrupt fails to occur. 12.
PAGE 5
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04 and dsPIC33FJ128GPX02/X04 APPENDIX A: REVISION HISTORY Revision A (3/2008) This is the initial release of this document. Revision B (9/2008) Added reference to silicon revisions A2 and A3. Added silicon issues 8-10 (I2C), 11 (UART (UxE Interrupt)), 12 (UART (IrDA)), 13 (Comparator), 14 (Internal Voltage Regulator), 15 (Product Identification), 16 (PSV Operations) and 17-18 (ECAN). © 2008 Microchip Technology Inc.
PAGE 6
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04 and dsPIC33FJ128GPX02/X04 NOTES: DS80371B-page 6 © 2008 Microchip Technology Inc.
PAGE 7
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
PAGE 8
Worldwide Sales and Service AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://support.microchip.com Web Address: www.microchip.