Datasheet

dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
DS75018C-page 98  2011-2012 Microchip Technology Inc.
REGISTER 7-9: IFS5: INTERRUPT FLAG STATUS REGISTER 5
R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0
PWM2IF
(1)
PWM1IF — — — — — —
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0
— — — — — — — JTAGIF
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 PWM2IF: PWM2 Interrupt Flag Status bit
(1)
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 14 PWM1IF: PWM1 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 13-1 Unimplemented: Read as ‘0’
bit 0 JTAGIF: JTAG Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
Note 1: This bit is not implemented in dsPIC33FJ06GS001/101A devices.