Datasheet

dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
DS75018C-page 82  2011-2012 Microchip Technology Inc.
6.2 System Reset
There are two types of Reset:
• Cold Reset
• Warm Reset
A cold Reset is the result of a Power-on Reset (POR)
or a Brown-out Reset (BOR). On a cold Reset, the
FNOSC Configuration bits in the FOSC Configuration
register select the device clock source.
A warm Reset is the result of all the other Reset
sources, including the RESET instruction. On warm
Reset, the device will continue to operate from the
current clock source, as indicated by the Current
Oscillator Selection bits (COSC<2:0>) in the Oscillator
Control register (OSCCON<14:12>).
The device is kept in a Reset state until the system
power supplies have stabilized at appropriate levels
and the oscillator clock is ready. The sequence in
which this occurs is provided in Figure 6-2.
TABLE 6-1: OSCILLATOR DELAY
Oscillator Mode
Oscillator
Start-up Delay
Oscillator
Start-up Timer
PLL Lock Time Total Delay
FRC, FRCDIV16, FRCDIVN TOSCD
(1)
—— TOSCD
(1)
FRCPLL TOSCD
(1)
—TLOCK
(3)
TOSCD + TLOCK
(1,3)
XT TOSCD
(1)
TOST
(2)
—TOSCD + TOST
(1,2)
HS TOSCD
(1)
TOST
(2)
—TOSCD + TOST
(1,2)
EC — — — —
XTPLL T
OSCD
(1)
TOST
(2)
TLOCK
(3)
TOSCD + TOST + TLOCK
(1,2,3)
HSPLL TOSCD
(1)
TOST
(2)
TLOCK
(3)
TOSCD + TOST + TLOCK
(1,2,3)
ECPLL — — TLOCK
(3)
TLOCK
(3)
LPRC TOSCD
(1)
—— TOSCD
(1)
Note 1: TOSCD = Oscillator start-up delay (1.1 s max. for FRC, 70 s max. for LPRC). Crystal oscillator start-up
times vary with crystal characteristics, load capacitance, etc.
2: T
OST = Oscillator Start-up Timer (OST) delay (1024 oscillator clock period). For example, TOST = 102.4 s
for a 10 MHz crystal and TOST = 32 ms for a 32 kHz crystal.
3: T
LOCK = PLL lock time (1.5 ms nominal) if PLL is enabled.