Datasheet

 2011-2012 Microchip Technology Inc. DS75018C-page 77
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
5.5 Flash Memory Control Registers
REGISTER 5-1: NVMCON: FLASH MEMORY CONTROL REGISTER
R/SO-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0
WR
(1)
WREN
(1)
WRERR
(1)
— — — — —
bit 15 bit 8
U-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
— ERASE
(1)
— —NVMOP<3:0>
(1,2)
bit 7 bit 0
Legend: SO = Settable Only bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 WR: Write Control bit
(1)
1 = Initiates a Flash memory program or erase operation. The operation is self-timed and the bit is
cleared by hardware once operation is complete. This bit can only be set (not cleared) in software.
0 = Program or erase operation is complete and inactive
bit 14 WREN: Write Enable bit
(1)
1 = Enables Flash program/erase operations
0 = Inhibits Flash program/erase operations
bit 13 WRERR: Write Sequence Error Flag bit
(1)
1 = An improper program or erase sequence attempt or termination has occurred (bit is set
automatically on any set attempt of the WR bit)
0 = The program or erase operation completed normally
bit 12-7 Unimplemented: Read as ‘0’
bit 6 ERASE: Erase/Program Enable bit
(1)
1 = Performs the erase operation specified by NVMOP<3:0> on the next WR command
0 = Performs the program operation specified by NVMOP<3:0> on the next WR command
bit 5-4 Unimplemented: Read as ‘0’
bit 3-0 NVMOP<3:0>: NVM Operation Select bits
(1,2)
If ERASE = 1:
1111 = No operation
1101 = Erase general segment
0011 = No operation
0010 = Memory page erase operation
0001 = Reserved
0000 = Reserved
If ERASE =
0:
1111 = No operation
1101 = No operation
0011 = Memory word program operation
0010 = No operation
0001 = Reserved
0000 = Reserved
Note 1: These bits can only be reset on a Power-on Reset (POR).
2: All other combinations of NVMOP<3:0> are unimplemented.