Datasheet

dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
DS75018C-page 306  2011-2012 Microchip Technology Inc.
TABLE 25-37: I2C1 BUS DATA TIMING REQUIREMENTS (MASTER MODE)
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C  T
A  +85°C for Industrial
-40°C  T
A  +125°C for Extended
Param. Symbol Characteristic Min.
(1)
Max. Units Conditions
IM10 T
LO:SCL Clock Low Time 100 kHz mode TCY/2 (BRG + 1) — s
400 kHz mode T
CY/2 (BRG + 1) — s
1 MHz mode
(2)
TCY/2 (BRG + 1) — s
IM11 T
HI:SCL Clock High Time 100 kHz mode TCY/2 (BRG + 1) — s
400 kHz mode T
CY/2 (BRG + 1) — s
1 MHz mode
(2)
TCY/2 (BRG + 1) — s
IM20 T
F:SCL SDA1 and SCL1
Fall Time
100 kHz mode — 300 ns CB is specified to be
from 10 pF to 400 pF
400 kHz mode 20 + 0.1 C
B 300 ns
1 MHz mode
(2)
— 100 ns
IM21 T
R:SCL SDA1 and SCL1
Rise Time
100 kHz mode — 1000 ns CB is specified to be
from 10 pF to 400 pF
400 kHz mode 20 + 0.1 C
B 300 ns
1 MHz mode
(2)
— 300 ns
IM25 T
SU:DAT Data Input
Setup Time
100 kHz mode 250 — ns
400 kHz mode 100 — ns
1 MHz mode
(2)
40 — ns
IM26 T
HD:DAT Data Input
Hold Time
100 kHz mode 0 — s
400 kHz mode 0 0.9 s
1 MHz mode
(2)
0.2 — s
IM30 T
SU:STA Start Condition
Setup Time
100 kHz mode TCY/2 (BRG + 1) — s Only relevant for
Repeated Start
condition
400 kHz mode T
CY/2 (BRG + 1) — s
1 MHz mode
(2)
TCY/2 (BRG + 1) — s
IM31 T
HD:STA Start Condition
Hold Time
100 kHz mode TCY/2 (BRG + 1) — s After this period the
first clock pulse is
generated
400 kHz mode T
CY/2 (BRG + 1) — s
1 MHz mode
(2)
TCY/2 (BRG + 1) — s
IM33 T
SU:STO Stop Condition
Setup Time
100 kHz mode TCY/2 (BRG + 1) — s
400 kHz mode T
CY/2 (BRG + 1) — s
1 MHz mode
(2)
TCY/2 (BRG + 1) — s
IM34 T
HD:STO Stop Condition 100 kHz mode TCY/2 (BRG + 1) — ns
Hold Time 400 kHz mode T
CY/2 (BRG + 1) — ns
1 MHz mode
(2)
TCY/2 (BRG + 1) — ns
IM40 T
AA:SCL Output Valid
From Clock
100 kHz mode — 3500 ns
400 kHz mode — 1000 ns
1 MHz mode
(2)
— 400 ns
IM45 T
BF:SDA Bus Free Time 100 kHz mode 4.7 — s Time the bus must be
free before a new
transmission can start
400 kHz mode 1.3 — s
1 MHz mode
(2)
0.5 — s
IM50 C
B Bus Capacitive Loading — 400 pF
IM51 T
PGD Pulse Gobbler Delay 65 390 ns See Note 3
Note 1: BRG is the value of the I
2
C™ Baud Rate Generator. Refer to Section 19. “Inter-Integrated Circuit
(I
2
C™)” (DS70195) in the “dsPIC33F/PIC24H Family Reference Manual”.
2: Maximum pin capacitance = 10 pF for all I2C1 pins (for 1 MHz mode only).
3: Typical value for this parameter is 130 ns.