Datasheet

dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
DS75018C-page 278  2011-2012 Microchip Technology Inc.
TABLE 25-9: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS
DC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C  T
A  +85°C for Industrial
-40°C  TA  +125°C for Extended
Param. Symbol Characteristic Min. Typ.
(1)
Max. Units Conditions
V
IL Input Low Voltage
DI10 I/O Pins V
SS —0.2VDD V
DI15 MCLR
VSS —0.2VDD V
DI16 I/O Pins with OSC1 V
SS —0.2VDD V
DI18 SDA1, SCL1 V
SS — 0.3 VDD V SMBus disabled
DI19 SDA1, SCL1 V
SS — 0.8 V SMBus enabled
V
IH Input High Voltage
DI20
DI21
I/O Pins Not 5V Tolerant
(4)
I/O Pins 5V Tolerant
(4)
0.7 VDD
0.7 VDD
—
—
VDD
5.5
V
V
DI28
DI29
SDA1, SCL1
SDA1, SCL1
0.7 V
DD
2.1
—
—
5.5
5.5
V
V
SMBus disabled
SMBus enabled
ICNPU CNx Pull-up Current
DI30 — 250 — AV
DD = 3.3V, VPIN = VSS
IIL Input Leakage Current
(2,3,4)
DI50 I/O Pins:
4x Sink Driver Pins
RA0-RA2, RB0-RB2, RB5-RB10,
RB15
16x Sink Driver Pins
RA3, RA4, RB3, RB4, RB11-RB14
—
—
—
—
±2
±8
A
A
V
SS  VPIN  VDD,
Pin at high-impedance
V
SS  VPIN  VDD,
Pin at high-impedance
DI55 MCLR
——±2AVSS VPIN VDD
DI56 OSC1 — — ±2 AVSS VPIN VDD,
XT and HS modes
Note 1: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated.
2: The leakage current on the MCLR
pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltages.
3: Negative current is defined as current sourced by the pin.
4: See the “Pin Diagrams” section for the list of 5V tolerant I/O pins.
5: V
IL source < (VSS – 0.3); characterized but not tested.
6: Non-5V tolerant pins V
IH source > (VDD + 0.3), 5V tolerant pins VIH source > 5.5V; characterized but not
tested.
7: Digital 5V tolerant pins cannot tolerate any “positive” input injection current from input sources > 5.5V.
8: Injection currents > | 0 | can affect the ADC results by approximately 4-6 counts.
9: Any number and/or combination of I/O pins, not excluded under I
ICL or IICH conditions, are permitted
provided the mathematical “absolute instantaneous” sum of the input injection currents from all pins do not
exceed the specified limit; characterized but not tested.