Datasheet

 2011-2012 Microchip Technology Inc. DS75018C-page 255
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
PLLKEN
PLL Lock Enable bit
1 = Clock switch to PLL source will wait until the PLL lock signal is valid
0 = Clock switch will not wait for the PLL lock signal
JTAGEN JTAG Enable bit
1 = JTAG is enabled
0 = JTAG is disabled
ICS<1:0> ICD Communication Channel Select bits
11 = Communicate on PGEC1 and PGED1
10 = Communicate on PGEC2 and PGED2
01 = Communicate on PGEC3 and PGED3
00 = Reserved, do not use
TABLE 22-3: dsPIC33F CONFIGURATION BITS DESCRIPTION (CONTINUED)
Bit Field Description