Datasheet

 2011-2012 Microchip Technology Inc. DS75018C-page 247
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
bit 5 EXTREF: Enable External Reference bit
(1)
1 = External source provides reference to DAC (maximum DAC voltage determined by external
voltage source)
0 = Internal reference sources provide reference to DAC (maximum DAC voltage determined by
RANGE bit setting)
bit 4 HYSPOL: Comparator Hysteresis Polarity Select bit
(1)
1 = Hysteresis is applied to the falling edge of the comparator output
0 = Hysteresis is applied to the rising edge of the comparator output
bit 3 CMPSTAT: Current State of Comparator Output Including CMPPOL Selection bit
(1)
bit 2 HGAIN: DAC Gain Enable bit
(1)
1 = Reference DAC output to comparator is scaled at 1.8x
0 = Reference DAC output to comparator is scaled at 1.0x
bit 1 CMPPOL: Comparator Output Polarity Control bit
(1)
1 = Output is inverted
0 = Output is non-inverted
bit 0 RANGE: Selects DAC Output Voltage Range bit
(1)
1 = High Range: Max DAC Value = AVDD/2, 1.65V at 3.3V AVDD
0 = Low Range: Max DAC Value = INTREF
(3)
REGISTER 20-1: CMPCONx: COMPARATOR CONTROL x REGISTER (CONTINUED)
Note 1: This bit is not implemented in dsPIC33FJ06GS101A/102A devices.
2: DACOUT can be associated only with a single comparator at any given time. The software must ensure
that multiple comparators do not enable the DAC output by setting their respective DACOE bit.
3: For the INTREF value, refer to the DAC Module Specifications (Table 25-42) in Section 25.0 “Electrical
Characteristics”.