Datasheet

 2011-2012 Microchip Technology Inc. DS75018C-page 245
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
20.8 Hysteresis
An additional feature of the module is hysteresis con-
trol. Hysteresis can be enabled or disabled and its
amplitude can be controlled by the HYSSEL<1:0> bits
in the CMPCONx register. Three different values are
available: 15 mV, 30 mV and 45 mV. It is also possible
to select the edge (rising or falling) to which hysteresis
is to be applied.
Hysteresis control prevents the comparator output from
continuously changing state because of small
perturbations (noise) at the input (see Figure 20-2).
FIGURE 20-2: HYSTERESIS CONTROL
20.9 Interaction with I/O Buffers
If the module is enabled and a pin has been selected
as the source for the comparator, then the chosen I/O
pad must disable the digital input buffer associated
with the pad to prevent excessive currents in the digital
buffer due to analog input voltages.
20.10 DAC Output Range
The DAC has a limitation for the maximum reference
voltage input of (AVDD – 1.5) volts. An external
reference voltage input should not exceed this value or
the reference DAC output will become indeterminate.
20.11 Analog Comparator Registers
The high-speed analog comparator module is
controlled by the following registers:
• CMPCONx: Comparator Control x Register
• CMPDACx: Comparator DAC Control x Register
Output
Input
Hysteresis Range
(15 mV/30 mV/45 mV)