Datasheet

dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
DS75018C-page 244  2011-2012 Microchip Technology Inc.
20.3 Module Applications
This module provides a means for the SMPS dsPIC
DSC devices to monitor voltage and currents in a
power conversion application. The ability to detect
transient conditions and stimulate the dsPIC DSC
processor and/or peripherals, without requiring the
processor and ADC to constantly monitor voltages or
currents, frees the dsPIC DSC to perform other tasks.
The comparator module has a high-speed comparator,
an associated 10-bit DAC and a DAC output amplifier
that provide a programmable reference voltage to the
inverting input of the comparator. The polarity of the
comparator output is user-programmable. The output
of the module can be used in the following modes:
• Generate an Interrupt
• Trigger an ADC Sample and Convert Process
• Truncate the PWM Signal (current limit)
• Truncate the PWM Period (current minimum)
• Disable the PWM Outputs (Fault latch)
The output of the comparator module may be used in
multiple modes at the same time, such as: 1) generate
an interrupt, 2) have the ADC take a sample and con-
vert it, and 3) truncate the PWM output in response to
a voltage being detected beyond its expected value.
The comparator module can also be used to wake-up
the system from Sleep or Idle mode when the analog
input voltage exceeds the programmed threshold
voltage.
20.4 DAC
The range of the DAC is controlled via an analog
multiplexer that selects either AVDD/2, an internal
reference source, INTREF, or an external reference
source, EXTREF. The full range of the DAC (AV
DD/2)
will typically be used when the chosen input source pin
is shared with the ADC. The reduced range option
(INTREF) will likely be used when monitoring current
levels using a current sense resistor. Usually, the
measured voltages in such applications are small
(<1.25V); therefore, the option of using a reduced
reference range for the comparator extends the
available DAC resolution in these applications. The
use of an external reference enables the user to
connect to a reference that better suits their
application.
DACOUT, shown in Figure 20-1, can only be
associated with a single comparator at a given time.
20.5 DAC Buffer Gain
The output of the DAC is buffered/amplified via the
DAC buffer. The block functions as a 1x gain amplifier
or as a 1.8x gain amplifier. The gain selection is con-
trolled via the HGAIN bit in the CMPCONx register.
Using the 1.8x gain option will raise the reference
voltage to the analog comparator to a maximum of
2.8V. Using a higher reference voltage for the analog
comparator can improve the signal-to-noise ratio in an
application.
20.6 Comparator Input Range
The comparator has an input voltage range from -0.2V
to AV
DD + 0.2V, making it a rail-to-rail input.
20.7 Digital Logic
The CMPCONx register (see Register 20-1) provides
the control logic that configures the High-Speed Analog
Comparator module. The digital logic provides a pulse
stretcher. The analog comparator can respond to very
fast transient signals. After the comparator output is
given the desired polarity, the signal is passed to this
pulse stretching circuit. The pulse stretching circuit has
an asynchronous set function and a delay circuit that
insure the minimum pulse width is three system clock
cycles wide so that the attached circuitry can properly
respond.
The stretch circuit is followed by a digital filter. The
digital filter is enabled via the FLTREN bit in the
CMPCONx register. The digital filter operates with the
clock specified via the FCLKSEL bit in the CMPCONx
register. The comparator signal must be stable in a high
or low state for at least three of the selected clock
cycles for it to pass through the digital filter.
During Sleep mode, the clock signal inputs to the
module are disabled. However, the module’s analog
components may continue to function in a reduced
power manner to allow the user to wake-up the device
when a signal is applied to a comparator input.
In Sleep mode, the clocks are stopped; however, the
analog comparator signal has an asynchronous con-
nection across the filter that allows interrupts to be
generated regardless of the stopped clocks.
The comparator can be disabled while in Idle mode if
the CMPSIDL bit is set. If a device has multiple compar-
ators, and any CMPSIDL bit is set, the entire group of
comparators will be disabled while in Idle mode. The
advantage is reduced power consumption. Moreover,
this behavior reduces complexity in the design of the
clock control logic for this module.
Note: It should be ensured in software that
multiple DACOE bits are not set. The
output on the DACOUT pin will be indeter-
minate if multiple comparators enable the
DAC output.