Datasheet

2011-2012 Microchip Technology Inc. DS75018C-page 243
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
20.0 HIGH-SPEED ANALOG
COMPARATOR
The high-speed analog comparator module monitors
current and/or voltage transients that may be too fast
for the CPU and ADC to capture.
20.1 Features Overview
The SMPS comparator module offers the following
major features:
Eight selectable comparator inputs
Up to two analog comparators
10-bit DAC for each analog comparator
Programmable output polarity
Interrupt generation capability
DACOUT pin to provide DAC output
DACOUT amplifier (1x, 1.8x)
Selectable hysteresis
DAC has three ranges of operation:
-AV
DD/2
- Internal Reference (INTREF)
- External Reference (EXTREF)
ADC sample and convert trigger capability
Disable capability reduces power consumption
Functional support for PWM module:
- PWM duty cycle control
- PWM period control
- PWM Fault detect
20.2 Module Description
Figure 20-1 shows a functional block diagram of one
analog comparator from the high-speed analog
comparator module. The analog comparator provides
high-speed operation with a typical delay of 20 ns. The
comparator has a typical offset voltage of ±5 mV. The
negative input of the comparator is always connected
to the DAC circuit. The positive input of the comparator
is connected to an analog multiplexer that selects the
desired source pin.
The analog comparator input pins are typically shared
with pins used by the Analog-to-Digital Converter
(ADC) module. Both the comparator and the ADC can
use the same pins at the same time. This capability
enables a user to measure an input voltage with the
ADC and detect voltage transients with the
comparator.
FIGURE 20-1: HIGH-SPEED ANALOG COMPARATOR MODULE BLOCK DIAGRAM
Note 1: This data sheet summarizes the features
of the dsPIC33FJ06GS001/101A/102A/
202A and dsPIC33FJ09GS302 families
of devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 45. “High-Speed
Analog Comparator” (DS70296) in the
“dsPIC33F/PIC24H Family Reference
Manual”, which is available on the
Microchip web site (www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
CMPxA
(1)
CMPxC
(1)
DAC
CMPPOL
0
1
AVDD/2
INTREF
(2)
M
U
X
M
U
X
CMREF
CMPx
(1)
INSEL<1:0>
10
Interrupt Request
CMPxB
(1)
CMPxD
(1)
Pulse Stretcher
EXTREF
(2)
Trigger to PWM
AVSS
and
RANGE
DACOUT
DACOE
Note 1: x = 1 and 2.
2: For the INTREF and EXTREF values, refer to the DAC Module Specifications (Table 25-42) in Section 25.0
“Electrical Characteristics”.
3: The output buffer is shared between the DACs and only one DAC can be enabled to drive this buffer.
Status
Digital Filter
HGAIN
Output
Buffer
(3)
AMP