Datasheet

dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302

DS75018C-page 240  2011-2012 Microchip Technology Inc.

(1)

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

IRQEN6 PEND6 SWTRG6

TRGSRC6<4:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-8 Unimplemented: Read as ‘0’

bit 7 IRQEN6: Interrupt Request Enable 6 bit

1 = Enable IRQ generation when requested conversion of channels AN13 and AN12 is completed

0 = IRQ is not generated

bit 6 PEND6: Pending Conversion Status 6 bit

1 = Conversion of channels AN13 and AN 12 is pending; set when selected trigger is asserted

0 = Conversion is complete

bit 5 SWTRG6: Software Trigger 6 bit

1 = Starts conversion of AN13 (INTREF) and AN12 (EXTREF) if selected by TRGSRC bits

(2)

This bit is automatically cleared by hardware when the PEND6 bit is set.

0 = Conversion has not started

Note 1: If other conversions are in progress, conversion will be performed when the conversion resources are

available.

2: AN13 is internally connected to Vref in all devices. AN12 is internally connected to the EXTREF pin in the

dsPIC33FJ06001/202A and dsPIC33FJ09GS302 devices. The dsPIC33FJ06GS101A/102A devices not

have an EXTREF pin; therefore, any data read on the corresponding AN12 input will be invalid.