Datasheet

 2011-2012 Microchip Technology Inc. DS75018C-page 237
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
bit 7 IRQEN0: Interrupt Request Enable 0 bit
1 = Enables IRQ generation when requested conversion of channels AN1 and AN0 is completed
0 = IRQ is not generated
bit 6 PEND0: Pending Conversion Status 0 bit
1 = Conversion of channels AN1 and AN0 is pending; set when selected trigger is asserted
0 = Conversion is complete
bit 5 SWTRG0: Software Trigger 0 bit
1 = Starts conversion of AN1 and AN0 (if selected by the TRGSRCx bits)
(1)
This bit is automatically cleared by hardware when the PEND0 bit is set.
0 = Conversion has not started
bit 4-0 TRGSRC0<4:0>: Trigger 0 Source Selection bits
Selects trigger source for conversion of analog channels AN1 and AN0.
11111 = Timer2 period match
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11011 = Reserved
11010 = PWM Generator 4 current-limit ADC trigger
11001 = Reserved
11000 = PWM Generator 2 current-limit ADC trigger
10111 = PWM Generator 1 current-limit ADC trigger
10110 = Reserved
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10010 = Reserved
10001 = PWM Generator 4 secondary trigger is selected
10000 = Reserved
01111 = PWM Generator 2 secondary trigger is selected
01110 = PWM Generator 1 secondary trigger is selected
01101 = Reserved
01100 = Timer1 period match
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01000 = Reserved
00111 = PWM Generator 4 primary trigger is selected
00110 = Reserved
00101 = PWM Generator 2 primary trigger is selected
00100 = PWM Generator 1 primary trigger is selected
00011 = PWM Special Event Trigger is selected
00010 = Global software trigger is selected
00001 = Individual software trigger is selected
00000 = No conversion is enabled
REGISTER 19-5: ADCPC0: ADC CONVERT PAIR CONTROL REGISTER 0 (CONTINUED)
Note 1: The trigger source must be set as a global software trigger prior to setting this bit to ‘1’. If other conversions
are in progress, then conversion will be performed when the conversion resources are available.