Datasheet

dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
DS75018C-page 234  2011-2012 Microchip Technology Inc.
REGISTER 19-3: ADBASE: ADC BASE REGISTER
(1)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
ADBASE<15:8>
(2)
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0
ADBASE<7:1>
(2)
—
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-1 ADBASE<15:1>: ADC Base Register bits
(2)
This register contains the base address of the user’s ADC Interrupt Service Routine (ISR) jump table.
This register, when read, contains the sum of the ADBASE register contents and the encoded value
of the PxRDY status bits.
The encoder logic provides the bit number of the highest priority PxRDY bits, where P0RDY is the
highest priority and P6RDY is the lowest priority.
bit 0 Unimplemented: Read as ‘0’
Note 1: As an alternative to using the ADBASE register, the ADCP0-6 ADC Pair Conversion Complete Interrupts
can be used to invoke A to D conversion completion routines for individual ADC input pairs.
2: The encoding results are shifted left two bits, so bits 1-0 of the result are always zero.